Ioannis Messaris

Hot carrier degradation modeling of short-channel n-FinFETs suitable for circuit simulators

Figure 1(a) shows the degradation of the transfer characteristics of a typical FinFET with W_fin = 10 nm, measured at V_d = 0.03 V after HC stress at V_stress = 1.8 V for different stress times. The degradation of the device parameters V_t, η and on-state drain current is clearly observed. The positive V_t shift indicates the built-up of a negative charge in the gate dielectric. The negative charge can result either from electron trapping in the gate dielectric or from generation of acceptor-type interface traps. Figure 1(b) shows the transconductance g_m degradation during HC stress. Degradation of the maximum g_m is observed attributed to the interface degradation, with a simultaneous parallel g_m shift due to charge injection into the gate dielectric bulk defects [4]. Using the relation SS=(kT/q).qD_it/C_ox for the subthreshold slope SS, where C_ox is the gate oxide capacitance and kT is the thermal energy, from figure 1(a) the extracted interface trap density D_it changes from 4×10¹² to 5.5×10¹²cm^-2eV^-1.

A study for replacing CMOS gates by equivalent inverters

Analysis of the operation of CMOS gates is a complicated procedure. These gates can be replaced by equivalent inverters and therefore the expressions for the inverters are used to determine the electrical characteristics of the gates. In this paper, the equivalent inverter approach for replacing CMOS gates is evaluated. The NAND gate is used for this evaluation. Parametric expressions are created to determine the transistors widths of the equivalent inverter. A systematic method is used for incorporating the parameter dependencies in the expressions. Results verify the accuracy of this approach.

An analytical model for the CMOS inverter

A new analytical model for the CMOS inverter is introduced. This model results by solving analytically the differential equation which describes the inverter operation. It uses new simplified transistor current expressions which are developed taking into account the nanoscale effects and also considering temperature as a parameter. Expressions for the output voltage are derived, which are then used for capturing the output and supply currents, making the model compatible with CCS technology requirements. The proposed model is parametric according to the input signal slew, output load, transistor widths, supply voltage, temperature and process parameters. It presents an average error less than 3% for the typical case.

Static gate power consumption model based on power contributors

Accurate and fast estimation of the static power consumption in various design corners for nanoscale integrated circuits is a very important task since it facilitates power and noise analysis procedures. The power contributor approach which is based on the separability of the power components can be used for this purpose. In this paper, parametric models for the power contributor currents are produced for the cells of an industry oriented library. Using these models, the power contributor method is evaluated for the estimation of the total static power consumption of the library cells. The models produced are expressed as a function of the power supply voltage, temperature and the transistor width. Results show that the proposed model estimations present an average error of about 0.4% while the maximum error remains less than 2% for all the design corners of the tested cells.

A data-driven Verilog-A ReRam model

The translation of emerging application concepts that exploit resistive random access memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models. Here, we present a ReRAM model, where device current–voltage characteristics and resistive switching rate are expressed as a function of: 1) bias voltage and 2) initial resistive state (RS). The model versatility is validated on detailed characterization data, for both filamentary valence change memory and nonfilamentary ReRAM technologies, where device resistance is swept across its operating range using multiple input voltage levels. Furthermore, the proposed model embodies a window function which features a simple mathematical form analytically describing RS response under constant bias voltage as extracted from physical device response data. Its Verilog-A implementation captures the ReRAM memory effect without requiring integration of the model state variable, making it suitable for fast and/or large-scale simulations and overall interoperable with current design tools.

A TiO2 ReRAM parameter extraction method

In this work, we present a parameter extraction method for TiO2 memristive devices that applies on a resistive switching rate model which embodies only four parameters for each voltage biasing polarity. The simple form of the model functions allows the derivation of a predictive analytical resistive state response expression under constant bias voltage. By employing corresponding experimental testing on the devices, we fit such constant bias responses exhibited by physical memristor samples on this analytical expression. Next, we apply a simple algorithm that extracts the suitable model parameters that capture the switching rate behavior of the characterized device in its voltage range of operation.

Modeling leakage currents of different CMOS cells by the power contributors method

This paper illustrates the Power Contributors method into modeling of leakage currents and static power consumption for different CMOS cells from the NanGate OpenCell library. These cells are decomposed into Power Contributors, and all the leakage currents which run through their terminals, are modeled in a systematic way. The results prove that this method facilitates the modeling procedures, without sacrificing their accuracy.

Variability analysis — Prediction method for nanoscale triple gate FinFETs

Our analytical compact model for the drain of undoped or lightly doped nanoscale FinFETs has been expanded in order to predict and decompose variability in the electrical characteristics of FinFETs. The model has been evaluated by comparison to TCAD simulated devices with predefined variability. Successful application to experimental data of FinFETs with fin width W_fin= 15 nm, gate length L_G =30 nm, equivalent gate oxide thickness t_ox = 1.7 nm and fin height H_fin= 65 nm, has attributed their behavior to geometrical variations (σL_G = 3.85 nm, σW_fin = 1.80 nm) and variability in the metal gate work function (σΦ_m = 48.1 eV).

An Evaluation of the Equivalent Inverter Modeling Approach

Accurate modeling of CMOS logic gates for timing and power characterization is a very important task in integrated circuits technology since it facilitates significantly the design phase. Parametric models provide flexibility in determining the circuit performance in various design corners. However, the direct analysis of a complex CMOS gate aiming in an analytical and parametric model is a difficult and cumbersome task. An alternative way to model these gates is by using the equivalent inverter approach. According to this, an inverter with appropriate transistor widths is defined in order to present the same response with the complex gate it models. The challenge with this approach is to propose a simple method to predict the appropriate transistor widths of the equivalent inverter. Then, an analytical model for the CMOS inverter can be used to provide estimates for the complex gates. In this paper, a macro-modeling method is proposed for determining the transistor widths of the equivalent inverter and a technique for providing parametric expressions for these widths in terms of input transition time, output capacitive load, initial transistor width, supply voltage and temperature. A tool is developed to provide timing and power characterizations for the cells of a digital cell library, much faster than conventional numerical circuit simulators. The results prove the efficiency of the equivalent inverter approach in modeling complex gates.

An analytical delay model for ReRAM memory cells

In this paper, we present a simple analytical delay model for memristive memory cells. The output voltage evolution is obtained analyzing the charge-flux dynamics when a voltage ramp is applied to the input. From this evolution, the propagation delay is calculated. The model is validated using the VTEAM memristor model for different input rise time values of the applied ramp. The proposed model can be used for accurate estimations of the dynamic behavior of huge ReRAM circuits when included in event-driven simulators.