Rathish Jayabharathi

SpeedGrade: an RTL path delay fault simulator

In the past, research on delay fault testing has been focused on test generation using various delay fault models on full scan gate level netlists. These tests are not very suitable for speed-binning since the confidence that the slowest paths have been covered is low. We have developed a novel methodology with an accompanying tool flow called SpeedGrade that performs path delay fault simulation using an RTL (Register Transfer Level) simulator. This novel method was used to translate the gate level path excitation conditions into higher level of abstraction without loss of accuracy. The higher efficiency of the RTL-based solution allowed for fault grading of functional patterns against the top critical paths in commercial microprocessor designs. The RTL-based approach also had the added benefit of being easier to use for debugging critical paths.

Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model

A novel function-based method for error propagation is proposed for exact delay fault coverage, using a single rated clock for fault activation under any delay fault model. Sequential circuits without full scan are considered. A latched error at a flip-flop represents one or more delay faults and is allowed to propagate to an observable point with or without the support of other latched errors. Existing methods allow only one flip-flop to have an error during the propagation phase to simplify the process of error propagation at the expense of decreased fault coverage. The advantage of the proposed method is demonstrated experimentally using the path-delay-fault model with more than 20% improvement in fault coverage

A novel solution for chip-level functional timing verification

Existing timing verification tools can provide methodologies for identifying and optimizing critical true paths in a embedded combinational module; however the problem of justifying these paths to the chip level is a very difficult one. This paper addresses the problem of timing verification at the entire chip level. We use a critical path tool, CRITIC, to obtain critical paths in an embedded combinational module. In order to reduce the complexity of checking whether the module-level critical path is indeed critical at the chip level, we use techniques from formal verification to extract the control behavior of the circuit, and check whether there is any control sequence which will justify the path to the chip level. The results of the experiments on several processor designs show that our approach is very effective in large sequential circuits such as microprocessors, where conventional ATPG techniques require inordinate amounts of CPU time. The experiments also show that the execution time remains reasonable as the circuit size increases, since we deal with a reduced control space rather than the entire state space of the circuit.

Non-enumerative generation of statistical path delays for ATPG

A Monte Carlo based approach capable of identifying the probability distributions that describe the delay of every sensitizable path in a path implicit manner is proposed. It is shown experimentally that the statistical information for all paths is generated as fast as the traditional Monte Carlo simulation that identifies the probability density function for the circuit delay.

Non-enumerative correlation-aware path selection

The path delay fault model is effective in detecting small delay defects. The proposed approach identifies the delay behavior of paths in various circuit instances without enumerating them. It selects critical paths through path implicit operations on a compact data structure potentially containing an exponential number of path candidates. The experimental analysis on some of the largest ISCAS-89 and ITC-99 benchmarks shows that the proposed approach is highly scalable and effective.

Implicit and Exact Path Delay Fault Grading in Sequential Circuits

The first path implicit and exact non-robust path delay fault grading technique for non-scan sequential circuits is presented. Non enumerative exact coverage is obtained, by allowing any latched error representing a delayed transition to propagate to a primary output with the support of other potentially latched errors. The generalized error propagation is done by symbolic simulation. Appropriate data structures for function manipulation are used. The advantage of the proposed method is demonstrated experimentally with consistent improvement in coverage over an existing pessimistic heuristic despite enforced bounds on the memory requirements.

FzCRITIC-a functional timing verifier using a novel fuzzy delay model

Chip performance and density are increasing tremendously and the CAD tools are always lagging behind. In this paper, we introduce a functional timing verifier using a novel fuzzy delay model which bridges the gap between the front-end timing verification and the back-end delay fault testing. The proposed fuzzy delay model can handle uncertainties with respect to timing characteristics, and manufacturing anomalies. Experimental results are presented for the ISCAS-85 benchmark circuits.

Non-enumerative Generation of Path Delay Distributions and Its Application to Critical Path Selection

A Monte Carlo-based approach is proposed capable of identifying in a non-enumerative and scalable manner the distributions that describe the delay of every path in a combinational circuit. Furthermore, a scalable approach to select critical paths from a potentially exponential number of path candidates is presented. Paths and their delay distributions are stored in Zero Suppressed Binary Decision Diagrams. Experimental results on some of the largest ISCAS-89 and ITC-99 benchmarks shows that the proposed method is highly scalable and effective.

Hybrid 3D pre-bonding test framework design

We have proposed in this paper a hybrid wireless test framework for pre-bond testing of 3D-SICs. This framework exploits high data rate & low noise near field inductive coupling mechanism for test data transfer. Test stimuli for IP cores and test control for TSV BIST are wirelessly transmitted through the probe card. Test responses from IP cores and TSV BIST are relayed back to the probe card by WiPads. A scheduling heuristic was further proposed for parallel testing of TSVs and IP cores, achieving reasonably close testing times to LB.

Exact At-speed Delay Fault Grading in Sequential Circuits

This paper examines the problem of exact delay fault grading in non-scan sequential circuits using a sequence of test patterns that are applied with a rated clock. Delay faults ending at flip-flops are latched as uncorrelated errors. The errors latched on flip-flops by previous tests may enhance the at-speed delay fault coverage for each pattern in the sequence. In addition, the propagation of errors (and the faults they represent) may be facilitated by other latched errors as well as potential delayed transitions activated by each at-speed test application. An exact grading method is presented and its impact over existing methods is demonstrated experimentally