Sreeker Dundigal

Integrated CMOS Sensor Array for Optical Heterodyne Phase Sensing

A heterodyne interferometric CMOS 8 × 8 phase sensor array was developed to measure the spatial phase distribution of an optical wavefront. This sensor is suitable for measuring rapidly changing surface profiles and characterizing fast turbulence. Using an acousto-optic modulation frequency of 80 MHz and beat frequency of 10 kHz, the system calculates 8-bit phase data at each location in the array at a rate equal to the beat frequency. The phase computation is performed locally, digitized, and stored in 8-bit SRAM. Implemented in a 0.5-μm 2P3M CMOS process, the measured RMS phase error is 1.49° (1 LSB) and mismatch has σ = 4.76° (3.4 LSB). Experimental results, in agreement with theory, validate the proposed approach.

Analog/mixed-signal design challenges in 7-nm CMOS and beyond

The economics of CMOS scaling remain lucrative with 7-nm mobile SoCs expected to be commercialized in 2018. Driven by careful design/technology co-optimization, modest reduction in fin, gate, and interconnect pitch as well as process innovations continue to offer compelling node-to-node power, performance, area, and cost benefits to advance logic and SRAM to the next foundry node. However, analog/mixed-signal circuits do not fully realize these improvements. They become more cumbersome to design, having worse parasitic resistance and capacitance, stronger layout-dependent effects, and layout growth in some situations. Furthermore, early adopters of these cutting-edge finFET nodes must cope with the complications of design concurrent with technology development for shorter product time-to-market. We provide an overview of the key process technology elements enabling 7 nm and beyond to address analog/mixed-signal design challenges. From this insight, we offer layout guidelines aimed to reduce design vulnerability to technology and model immaturity.

Analog/Mixed-Signal Design in FinFET Technologies

Consumer demand for low-power mobile ICs has propelled CMOS scaling to arrive at the fully depleted finFET with foundry offerings already available at 16/14, 10, and 7 nm. The compact three-dimensional structure of the finFET offers superior short-channel control that achieves digital power reduction while increasing device performance for a given area. As system-on-chip technology remains driven by logic and SRAM scaling needs, designers of analog/mixed-signal subsystems must continue to adapt to new technology constraints. We attempt to summarize the challenges and technology considerations encountered when we port analog/mixed-signal designs to a finFET node. At 16/14 nm and beyond, designers also face many implications from scaling innovations leading to the finFET.