Sridhar Narayanan

Reconfiguration techniques for a single scan chain

A major drawback in using scan techniques is the long test application times incurred in shifting test data in and out of a device. This problem assumes even greater significance with the rapid growth in both the number of test patterns and scan registers occurring in complex VLSI designs. This paper presents a novel methodology based on reconfiguring a single scan chain to minimize the shifting time in applying test patterns to a device. The main idea is to employ multiplexers to bypass registers that are not frequently accessed in the test process and hence reduce the overall test application time, For partitioned scan designs, we describe two different modes of test application which can be used to efficiently tradeoff the logic and routing overheads of the reconfiguration strategy with the test application time. In each case we provide detailed analysis and optimization techniques to minimize the number of added multiplexers and the corresponding test time. Implementation results on two data path circuits demonstrate test time reductions as large as 75% over traditional schemes at the expense of 1-3 multiplexers. >

A fault diagnosis methodology for the UltraSPARC/sup TM/-I microprocessor

In this paper we study the use of precomputed fault dictionaries to diagnose stuck-at and bridging defects in the UltraSPARC/sup TM/-I processor. In constructing the dictionary we analyze the effect of the dictionary format on parameters such as memory size, computational effort, and diagnostic resolution. The dictionary is built based on modeled stuck-at faults. However to effectively diagnose both stuck-at and bridging faults, we employ a novel procedure that combines dictionary information with potential bridge defects extracted from layout. Experiments with failing devices show excellent correlation of predicted errors with actual defects.