Srikanth Venkataraman

A technique for fault diagnosis of defects in scan chains

In this paper, we present a scan chain fault diagnosis procedure. The diagnosis for a single scan chain fault is performed in three steps. The first step uses special chain test patterns to determine both the faulty chain and the fault type in the faulty chain. The second step uses a novel procedure to generate special test patterns to identify the suspect scan cell within a range of scan cells. Unlike previously proposed methods that restrict the location of the faulty scan cell only from the scan chain output side, our method restricts the location of the faulty scan cell from both the scan chain output side and the scan chain input side. Hence the number of suspect scan cells is reduced significantly in this step. The final step further improves the diagnostic resolution by ranking the suspect scan cells inside this range. The proposed technique handles both stuck-at and timing failures (transition faults and hold time faults). The extension of the procedure to diagnose multiple faults is discussed. The experimental results show the effectiveness of the proposed method.

POIROT: a logic fault diagnosis tool and its applications

Logic fault diagnosis or fault isolation is the process of analyzing the failing logic portions of an integrated circuit to isolate the cause of failure. Fault diagnosis plays an important role in multiple applications at different stages of design and manufacturing. A logic diagnosis tool with applicability to a spectrum of logic DFT, ATPG and test strategies including full/almost fullscan circuits with combinational ATPG, partial-scan and non-scan circuits with sequential ATPG and to functional patterns in general is presented. Novel features incorporated into the tool include static and dynamic structural processing for partial-scan circuits, windowed fault simulation, and diagnostic models for open defects and cover algorithms for multiple fault diagnosis. Experimental results include simulation results on processor functional blocks and silicon results on chipsets and processors from artificially induced defects and production fallout.

Poirot: applications of a logic fault diagnosis tool

The Poirot tool isolates and diagnoses defects through fault modeling and simulation. Along with a carefully selected partitioning strategy, functional and sequential test pattern applications show success with circuits having a high degree of observability.

Automated Debug of Speed Path Failures Using Functional Tests

Debug of at-speed failures using functional tests is a key challenge as part of frequency pushes during post-silicon debug to improve performance of high performance designs, especially microprocessors. In this paper, we present a technique to automate the debug of speed path failures using failing functional tests by extracting information from design-for-debug features and then algorithmically isolating the internal speed-paths that could be the source of the failures. Results from application of the technique during silicon debug on the Intel ® Core ™ i7 quad-core processor is presented.

A technique for logic fault diagnosis of interconnect open defects

A technique to perform logic diagnosis of defects that cause interconnects in a digital logic circuit to become open or highly resistive is presented. The novel features of this work include a diagnostic fault model to capture potential faulty behaviors in the presence of an open defect and diagnosis algorithms that leverage the diagnostic model while circumventing the need for detailed circuit-level (SPICE) simulation and extraction of parasitic capacitance. Other aspects of the technique include a path-tracing procedure to limit the number of interconnects that need to be analyzed and extensions for multiple defects. Experimental results include simulation results on processor functional blocks and silicon results on a chipset from artificially induced defects and production fallout.

An experimental study of N-detect scan ATPG patterns on a processor

This paper studies the impact of N-detect scan ATPG patterns on test quality and associated test costs. An incremental method for test generation is presented. Metrics to evaluate the richness of the test set are presented. The natural N-detect profiles of regular one-detect test sets and the impact to test data volume and test time of generating additional patterns is studied. Results are presented on an lntel/spl reg/ Pentium/spl reg/ 4 processor. Simulation results from evaluating the patterns on layout extracted and random bridges are presented. Silicon data from production test shows the effectiveness of N-detect tests.

Evaluation of the quality of N-detect scan ATPG patterns on a processor

This paper evaluates N-detect scan ATPG patterns for their impact to test quality through simulation and fallout from production on a Pentium 4 processor using 90 nm manufacturing technology. An incremental ATPG flow is used to generate N-detect test patterns. The generated patterns were applied in production with flows to determine overlap in fallout to different tests. The generated N-detect test patterns are then evaluated based on different metrics. The metrics include signal states, bridge fault coverage, stuck-at fault coverage and fault detection profile. The correlation between the different metrics is studied. Data from production fallout shows the effectiveness of N-detect tests. Further, the correlation between fallout data and the different metrics is analyzed.

Improving Precision Using Mixed-level Fault Diagnosis

For nanometer manufacturing fabrication process, it is critical to narrow down the defect location for successful physical failure analysis. This paper presents a mixed-level diagnosis technique, which first performs diagnosis at logic level, and then performs switch-level analysis to locate a defect at transistor level. An efficient single pass mixed-mode diagnosis flow proposed to isolate defects within a cell. Experimental results showed significant improvement in precision over traditional logic diagnosis with only a fractional increase in run-time. The proposed mixed-level diagnosis technique was applied to successfully isolate silicon defects

An algorithmic technique for diagnosis of faulty scan chains

This paper presents an algorithmic scan-chain-fault diagnosis procedure. The diagnosis for a single scan-chain fault is performed in three steps. The first step uses special chain test patterns to determine both the faulty chain and the fault type in the faulty chain. The second step uses a novel procedure to identify the suspect scan cell within a range of scan cells. The final step further improves the diagnostic resolution by ranking the suspect scan cells inside this range. The proposed technique handles both stuck-at and timing failures (transition faults and hold-time faults). The application of the procedure in a production test flow is discussed. Simulation and silicon results from several products show the effectiveness of the proposed method

Evaluation of test metrics: stuck-at, bridge coverage estimate and gate exhaustive

Production test data from more than 500,000 chips is analyzed to understand the correlation between the number of defective chips detected by a set of test patterns and the coverage values of these test patterns with respect to various test metrics. Experimental results show that the gate exhaustive metric has the highest correlation when compared to the stuck-at and the bridge coverage estimate metrics, especially for high coverage test patterns. More than 69% of all test patterns can be removed from the test set without reducing the number of detected chips - more than 99% of these patterns are required to obtain high stuck-at coverage. None of the test metrics are very effective in predicting which subset of a given set of test patterns can be removed from the test set without compromising test quality before the patterns are actually applied to manufactured ICs