Ruifeng Guo

Proptest: a property based test pattern generator for sequential circuits using test compaction

We describe a property based test generation procedure that uses static compaction to generate test sequences that achieve high fault coverages at a low computational complexity. A class of test compaction procedures are proposed and used in the property based test generator. Experimental results indicate that these compaction procedures can be used to implement the proposed test generator to achieve high fault coverage with relatively smaller run times.

Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration

We propose several compaction procedures for synchronous sequential circuits based on test vector restoration. Under a vector restoration procedure, all or most of the test vectors are first omitted from the test sequence. Test vectors are then restored one at a time or in subsequences only as necessary to restore the fault coverage of the original sequence. Techniques to speed-up the restoration process are investigated. These include limiting the test vectors initially omitted from the test sequence, consideration of several faults in parallel during restoration, and the use of a parallel fault simulator.

On speeding-up vector restoration based static compaction of test sequences for sequential circuits

We propose a technique to speed up restoration-based static test sequence compaction for synchronous sequential circuits. The proposed algorithm reverses the order of the test vectors during restoration. Specifically, every time a subsequence of T is restored to detect a subset of faults, the subsequence is placed at the end of the compacted sequence denoted by T/sub p/. In this way, a fault detected by T/sub p/ is guaranteed to remain detected by T/sub p/ at the end of the compaction process, and need not be resimulated as was the case with some of the earlier restoration based compaction methods. Experimental results presented in this paper demonstrate the effectiveness of the proposed procedure.

A fault simulation based test pattern generator for synchronous sequential circuits

We describe a fault simulation based test generation procedure for synchronous sequential circuits. Several techniques are used to generate test sequences to achieve high fault coverages at low computational complexity. Experimental results presented demonstrate that the proposed procedure achieves fault coverages which are in all cases the same or higher than those achieved by existing procedures. The run times of the procedure are considerably smaller compared to the existing procedures.

Diagnosis of Multiple Physical Defects Using Logic Fault Models

In this work, we propose a method to improve diagnosis results when multiple physical defects are present in circuits under diagnosis. To improve diagnosis results when multiple defects are present in a circuit under diagnosis, the proposed method includes (i) analyzing relations among locations of logic faults and their diagnostic metrics to carefully derive physical faults, (ii) a new set covering procedure and (iii) a method to assign scores to faults to derive candidate sets of faults. Experimental results on several industrial designs and several cases of silicon defects show the effectiveness of the proposed diagnosis method.

Reverse-order-restoration-based static test compaction for synchronous sequential circuits

We present a new static test sequence compaction procedure called reverse-order-restoration (ROR) for synchronous sequential circuits. It improves the efficiency of the basic vector restoration-based compaction procedure by reversing the order of the vectors in the original test sequence. This reduces the number of faults to be resimulated after every restoration step. We extend the ROR procedure to a class of radix reverse order vector restoration procedures. These procedures dynamically increase the number of vectors to be restored in each step and, thus, speed up the vector restoration process. We also investigate techniques to improve the compaction levels achieved by the ROR-based compaction procedure. By combining reverse order vector restoration and vector omission, higher compaction levels are achieved. Experimental results on test sequences generated by several test generators show the effectiveness of the proposed techniques.

On improving static test compaction for sequential circuits

The cost of testing a VLSI circuit is greatly affected by the length of its test sequence. Compaction techniques are often used to reduce the test sequence length. In this paper, we propose a new test sequence compaction procedure for synchronous sequential circuits aimed at improving the level of compaction compared to earlier efficient procedures. It is based on the reverse order restoration (ROR) compaction algorithm and the vector omission based compaction algorithm presented earlier. During vector restoration, once a subsequence is restored, the vector omission based method is applied to the restored subsequence to reduce the number of test vectors restored. Parallel pattern simulation for a single fault, as proposed earlier, is used to speed up the vector restoration process. Experimental results on test sequences generated by several test generators show the effectiveness of the proposed method in improving the level of compaction.

Static test compaction for synchronous sequential circuits based on vector restoration

We propose a new static test compaction procedure for synchronous sequential circuits. The procedure belongs to the class of procedures that omit test vectors from a given test sequence in order to reduce its length without reducing the fault coverage. The previous procedure that achieved high levels of compaction using this approach attempted to omit test vectors from a given test sequence one at a time or in subsequences of consecutive vectors. The omission of each vector or subsequence required extensive simulation to determine the effects of each omission on the fault coverage. The procedure proposed here first omits (almost) all the test vectors from the sequence, and then restores some of them as necessary to achieve the required fault coverage. The decision to restore a vector requires simulation of a single fault. Thus, the overall computational effort of this procedure is relatively low. The loss of compaction compared to the scheme that omits the vectors one at a time or in subsequences is small in most cases. Techniques to speed up the restoration process are also investigated, including consideration of several faults in parallel during restoration, and the use of a parallel fault simulator. Experimental results are presented to demonstrate the effectiveness of vector restoration as a static compaction technique.

The effects of test compaction on fault diagnosis

The effect of test compaction on fault diagnosis is experimentally investigated. Results for combinational and sequential circuits indicate that the diagnostic resolution achieved by compacted tests is only minimally lower than that for uncompacted tests. Furthermore, the diagnostic resolution of the compacted tests can be enhanced to be the same or better than that for the uncompacted rests while still retaining compactness.

Diagnosis of Multiple Faults Based on Fault-Tuple Equivalence Tree

In this work, new techniques are proposed to improve diagnosis of multiple faults based on fault-tuple equivalence tree (FTET). After carefully analyzing relations between faults in FTET, the concept of conflicts is proposed and utilized to locate the faulty sites. The proposed diagnosis algorithm can accurately identify the defect locations and also identify the physical fault types, which was demonstrated by experimental results on large ISCAS89 and ITC99 circuits.