Nagesh Tamarapalli

Logic BIST for large industrial designs: real issues and case studies

This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200 K to 800 K gates, pose significant challenges to logic BIST methodology, flow, and tools. The paper presents the process of generating a BIST-compliant core along with the logic BIST controller for at-speed testing. Comparative data on fault grades and area overhead between automatic test pattern generation (ATPG) and logic BIST are reported. The experimental results demonstrate that with automation of the proposed solutions, logic BIST can achieve test quality approaching that of ATPG with minimal area overhead and few changes to the design flow.

High-frequency, at-speed scan testing

The authors describe new strategies where at-speed scan tests can be applied with internal PLL. They present techniques for optimizing ATPG across multiple clock domains and methodologies to combine both stuck-at-fault and delay-test vectors into an effective test suite.

A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis

This paper presents a flow for using logic diagnosis to turn production material into vehicles for yield learning. High throughput logic diagnosis is combined with the newly emerging field of design for manufacturing to enable layout aware diagnosis. The ability of the flow to calculate feature failure rates and the application of the failure rates for yield learning is demonstrated through volume data analysis on a production ASIC

Diagnosis with Limited Failure Information

This paper discusses the challenges associated with diagnosing chain integrity and system logic failures in the production test environment with limited failure information. The following three methods were proposed to enhance diagnosis resolution in this scenario: (1) static pattern re-ordering (2) dynamic pattern re-ordering (3) per-pin based diagnosis. Experimental results illustrate that per-pin based failure logging and diagnosis algorithms enable scan chain diagnosis in volume production environment. Successful application of per-pin based chain diagnosis is demonstrated with an industrial case

Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis

As electronic design feature sizes continue to shrink and clock speeds continue to rise, more and more companies have turned to at-speed test techniques to help ensure high test and product quality. Due to incomplete timing information during automatic test pattern generation (ATPG), it is possible that some at-speed patterns may activate paths which are not required to meet system speed, and these patterns may fail during production test. It is often difficult and time consuming to identify these paths manually. This paper describes how to use diagnosis techniques to automatically identify these paths. Using this approach, the authors found most of these paths were false or multicycle paths inside DFT logic. These could be fixed by enhancing the timing exception paths used during ATPG to mask out transition values through these paths. Elimination of these paths resulted in a 300 MHz increase in the speed of the transition fault test pattern. However, occasionally the authors did find some failing paths were real functional problems and design changes were needed to resolve them

DFM / DFT / SiliconDebug / Diagnosis

Semiconductor yield has traditionally been limited by random particle-defect based issues. However, as the feature sizes reduced to 0.13 micron and below, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss. In addition, it is becoming clear that ramping yield would take longer and final yields would not reach historical norms. A key factor for not reaching previously attained yield levels is the interaction between design and manufacturing. Yield losses in the newer processes include functional defects, parametric defects and issues with testing. Each of these sources of yield loss needs to analyzed and understood by designers and tool developers. In addition, new techniques and methods must be devised to minimize the impact of these yield loss mechanisms. After an introduction of the issues involved in the first section, the second section covers Design-for-Manufacturing (DFM) techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield. However, once the changes are made it is necessary to quantify their impact so that knowledge about yield contribution of different features can be fed back to design and DFM tools. Test presents an opportunity to close the loop by crafting test patterns to expose the defect prone features during automatic test pattern generation (ATPG) and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact. The third section covers design techniques (DFX) to improve testability, debuggability and diagnosability, and DFM and defect aware test generation to both meet product quality and expose yield issues at test. Section four covers the basic concepts and theoretical aspects of debug and diagnosis including algorithmic IC diagnosis, scan chain diagnosis, critical path based techniques and diagnosis of delay defects. The applications of the basic concepts and techniques for silicon debug are covered in section five. Section six covers the application of statistical diagnosis techniques to determine the features that are actually causing yield loss and their relative impact. Finally, in section seven, future trends, challenges and directions are covered.

DFM, DFT, silicon debug and diagnosis -the loop to ensure product yield

Summary form only for tutorial. After an introduction of the issues involved in the first section, the second section covers design-for-manufacturing (DFM) techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield. However, once the changes are made it is necessary to quantify their impact so that knowledge about yield contribution of different features can be fed back to design and DFM tools. Test presents an opportunity to close the loop by crafting test patterns to expose the defect prone features during automatic test pattern generation (ATPG) and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact. The third section covers design techniques (DFX) to improve testability, debuggability and diagnosability, and DFM and defect aware test generation to both meet product quality and expose yield issues at test. Section four covers the basic concepts and theoretical aspects of debug and diagnosis including algorithmic IC diagnosis, scan chain diagnosis, critical path based techniques and diagnosis of delay defects. The applications of the basic concepts and techniques for silicon debug are covered in section five. Section six covers the application of statistical diagnosis techniques to determine the features that are actually causing yield loss and their relative impact. Finally, in section seven, future trends, challenges and directions are covered.

Achieving higher yield through diagnosis

With the continuous drive to smaller features, introduction of new manufacturing materials, sub-wavelength lithography, and process and design interaction, achieving acceptable yield at technology nodes 130 nm and below is proving to be a daunting task. At these technology nodes yield is limited not just by random defects but also increasingly by systematic yield detracting mechanisms. In addition, a larger portion of the defects are becoming non-visual and/or parametric in nature. In fact many defects that cause electrical failures are not detectable by the traditional defect sourcing techniques such as inline inspection