Srinivasa Banna

Vertical double gate Z-RAM technology with remarkable low voltage operation for DRAM application

Vertical double gate floating body (FB) Z-RAM memory cell technology fabricated on a recess gate DRAM technology is presented. Cell operating voltage of 0.5V with comparable static retention and > 1000x improvement in dynamic retention is reported. The reported vertical double gate FB cell is the cell with the lowest operation voltage reported to date.

Architecting advanced technologies for 14nm and beyond with 3D FinFET transistors for the future SoC applications

Industrys extensive knowledge of fabricating bulk CMOS planar transistors has made them the device of choice for the cost sensitive foundry semiconductor sector. On advanced nodes the scaling benefits for SoCs will be based on a set of Key Performance Indicators (KPIs) (Fig.1) quantified by measurable Figures of Merit (FOMs). These KPIs cover a range of requirements from system level performance, power, and die area scaling to manufacturing cost, production risk, reliability limitations, designabilty and technology extension for a broad domain of SoCs. Critical performance FOMs include Fmax, compute density performance at constant power density (MHz/mW/mm2) and performance vs. power for a given cost (PPC) (MHz/mW/

Power, performance, and cost comparisons of monolithic 3D ICs and TSV-based 3D ICs

). The idea is to integrate the transistor and physical scaling benefits to offer a cost sensitive technology platform that provides value for the SoC applications and effectively for the end users. Fig. 1 illustrates the complexity of achieving this task to minimize the risk and TTV/TTM while addressing the difficult technical barriers. Device and circuit co-optimization enhances the SoC values measured by PPC, PPA, and Fmax.

On the Design of Ultra-High Density 14nm Finfet Based Transistor-Level Monolithic 3D ICs

Power, performance, area, and cost analysis of TSV, mini-TSV, and monolithic 3D ICs is presented. Power savings for TSV, mini-TSV, and monolithic 3D ICs are 21%, 25%, and 37%, respectively, compared to that of a 2D IC. It is shown that monolithic 3D can deliver one node PPC benefit, whereas TSV 3D or mini-TSV 3D can only achieve a half node PPC advantage.

Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs

Conventional 2D CMOS faces severe challenges sub-22nm nodes. The monolithic 3D (M3D) IC technology enables ultra-high density vertical connections and provides a good path for technology node scaling. Transistor-level (TR-L) monolithic 3D IC is the most advanced and fine-grained M3D IC technology. In this paper, for the first time, the detailed design as well as benefits and challenges of a silicon validated 14nm Finfet process design kit (PDK) based TR-L M3D IC technology is explored. TR-L M3D standard cell layout is achieved based on 14nm Finfet design rules and feature sizes. A semi-customized RC extraction methodology is performed for accurate 3D cell RC extraction. After extensive simulation, TR-L M3D cell power, delay and area are evaluated and compared with equivalent 2D cells in the same technology node. System-level benchmarking with several circuits show up to 55% reduced footprint, 25% shorter wire length, and 18% lower power with TR-L M3D vs. 2D CMOS.

Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology

In this paper, we develop tier partitioning strategy to mitigate back-end-of-line (BEOL) interconnect delay degradation and cost issues in monolithic 3D ICs (M3D). First, we study the routing overhead and delay degradation caused by tungsten BEOL interconnect in the bottom-tier of M3D. Our study shows that tungsten BEOL reduces performance by up to 30% at 4× resistance increase of bottom-tier interconnect. In addition, the bottom-tier BEOL adds a routing overhead to 3D nets, which is neglected in the state-of-the-art flow. Next, we develop two partitioning methods targeted specifically towards BEOL impact reduction. Our path-based approach identifies critical timing paths and places their cells in the top-tier to reduce the impact of delay degradation and routing overhead. Our net-based partitioning methodology confines the nets with long 2D wirelength into the top-tier to reduce the overall routing demand, and hence the metal layer usage in the bottom-tier. This in turn results in BEOL cost savings. Using a foundry 22nm FDSOI technology and full-chip GDS designs, we achieve tolerance of up to 4× increase in the bottom-tier BEOL resistance using our partitioning strategy. In addition, we save up to 3 metal layers in the bottom-tier of our M3D designs with up to 32% power savings over 2D IC for an interconnect dominated benchmark.

How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions

In this paper, we conduct a comprehensive design comparison of 2D ICs, monolithic 3D ICs and TSV-based 3D ICs using a silicon-validated 14nm FinFET foundry technology and commercial quality designs. Through full-chip layouts and sign-off analysis using commercial-grade tools, the potential of monolithic 3D IC is explored and validated in terms of power, performance and area against that of TSV-based 3D ICs and 2D ICs.

A 14nm FinFET transistor-level 3D partitioning design to enable high-performance and low-cost monolithic 3D IC

In this paper we study the impact of low thermal budget process on design quality in monolithic 3D ICs (M3D). Specifically, we quantify how much the tier-to-tier transistor performance difference affects full-chip power and performance metrics in a foundry 14nm FinFET technology. Our study first shows that 5%, 10%, and 15% top-tier device degradation in a wire-dominated, timing-closed monolithic 3D IC design leads to 7%, 12%, and 18% full-chip timing violation, respectively. Next, we address this impact with our CAD solution named Tier-Aware M3D (TA-M3D) flow that identifies potential timing-critical paths and partitions them into the faster (bottom) tier to minimize the top-tier degradation impact. One unique challenge in timing closure in this case, is how to conduct buffering and sizing on the paths that lie entirely in the top or bottom-tier as well as those that span both tiers. Our approach handles all 3 types of paths carefully and closes timing under the given top-tier degradation assumption, while minimizing the total power consumption. Our enhanced monolithic 3D IC designs, even with 5%, 10%, and 15% slower transistors in the top-tier, still offers 26%, 24%, and 5% power savings over 2D IC, respectively. Our study also covers other types of circuits.

Design and process technology co-optimization with SADP BEOL in sub-10nm SRAM bitcell

Monolithic 3D IC (M3D) shows degradation in performance compared to 2D IC due to the restricted thermal budget during fabrication of sequential device layers. A transistor-level (TR-L) partitioning design is used in M3D to mitigate this degradation. Silicon validated 14nm FinFET data and models are used in a device-to-system evaluation to compare the TR-L partitioned M3Ds (TR-L M3D) performance against the conventional gate-level (G-L) partitioned M3Ds performance as well as standard 2D IC. Extensive cell-level and system-level evaluation, including various device and interconnect process options, shows that the TR-L M3D provides up to 20% improved performance while still maintaining around 30% power saving compared to standard 2D IC. Additionally, the TR-L partitioning design enables M3D with a simplified process flow that leads to 23% lower cost compared to that of G-L partitioning scheme.

Impact of gate oxide complex band structure on n-channel III–V FinFETs

Due to the resolution limit of the lithography tools, multiple patterning technologies are being introduced to the back-end of the line (BEOL). For example, LELELE (or LE3, triple litho-etch) or SADP (self-aligned double patterning) [1] are already implemented in 10nm node technology based on a polygons geometry, its orientation and pitch requirement. However, metal architecture, arrangement of signal and power lines in a metal layer or across metal layers, cause a significant impact on operating performance as well as determine the metals orientation, which is also an important element for lithographic performance. Therefore, all the factors should be addressed together to arrive at an optimal chip performance.