Srinivasa R. Sridhara

Coding for system-on-chip networks: a unified framework

Global buses in deep-submicron (DSM) system-on-chip designs consume significant amounts of power, have large propagation delays, and are susceptible to errors due to DSM noise. Coding schemes exist that tackle these problems individually. In this paper, we present a coding framework derived from a communication-theoretic view of a DSM bus to jointly address power, delay, and reliability. In this framework, the data is first passed through a nonlinear source coder that reduces self and coupling transition activity and imposes a constraint on the peak coupling transitions on the bus. Next, a linear error control coder adds redundancy to enable error detection and correction. The framework is employed to efficiently combine existing codes and to derive novel codes that span a wide range of tradeoffs between bus delay, codec latency, power, area, and reliability. Using simulation results in 0.13-/spl mu/m CMOS technology, we show that coding is a better alternative to repeater insertion for delay reduction as it reduces power dissipation at the same time. For a 10-mm 4-bit bus, we show that a bus employing the proposed codes achieves up to 2.17/spl times/ speed-up and 33% energy savings over a bus employing Hamming code. For a 10-mm 32-bit bus, we show that 1.7/spl times/ speed-up and 27% reduction in energy are achievable over an uncoded bus by employing low-swing signaling without any loss in reliability.

Reliable low-power digital signal processing via reduced precision redundancy

In this paper, we present a novel algorithmic noise-tolerance (ANT) technique referred to as reduced precision redundancy (RPR). RPR requires a reduced precision replica whose output can be employed as the corrected output in case the original system computes erroneously. When combined with voltage overscaling (VOS), the resulting soft digital signal processing system achieves up to 60% and 44% energy savings with no loss in the signal-to-noise ratio (SNR) for receive filtering in a QPSK system and the butterfly of fast Fourier transform (FFT) in a WLAN OFDM system, respectively. These energy savings are with respect to optimally scaled (i.e., the supply voltage equals the critical voltage V/sub dd-crit/) present day systems. Further, we show that the RPR technique is able to maintain the output SNR for error rates of up to 0.09/sample and 0.06/sample in an finite impulse response filter and a FFT block, respectively.

Microwatt embedded processor platform for medical system-on-chip applications

A medical system-on-chip (SoC) that integrates an ARM Cortex-M3 processor is presented. Ultra-low power operation is achieved via 0.5–1.0 V operation, a 28 fW/bit fully differential subthreshold 6T SRAM, a 90%-efficient DC-DC converter, and a 100-nJ fast Fourier transform (FFT) accelerator to reduce processor workload. Using a combination of novel circuit design, system architecture, and SoC implementation, the first sub-microwatt per channel electroencephalograph (EEG) seizure detection is demonstrated.

Area and energy-efficient crosstalk avoidance codes for on-chip buses

Capacitive crosstalk between adjacent wires in long on-chip buses significantly increases propagation delay in the deep submicron regime. A high-speed bus can be designed by eliminating crosstalk delay through bus encoding. In this paper, we present an overview of the existing coding schemes and show that they require either a large wiring overhead or complex encoder-decoder circuits. We propose a family of codes referred to as overlapping codes that reduce both overheads. We construct two codes from this family and demonstrate their superiority over existing schemes in terms of area and energy dissipation. Specifically, for a 1-cm 32-bit bus in 0.13-/spl mu/m CMOS technology, we present a 48-wire solution that has 1.98/spl times/ speed-up, 10% energy savings and requires 20% less area than shielding.

Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes

A reliable high-speed bus employing low-swing signaling can be designed by encoding the bus to prevent crosstalk and provide error correction. Coding for on-chip buses requires additional bus wires and codec circuits. In this paper, fundamental bounds on the number of wires required to provide joint crosstalk avoidance and error correction using memoryless codes are presented. The authors propose a code construction that results in practical codec circuits with the number of wires being within 35% of the fundamental bounds. When applied to a 10-mm 32-bit bus in a 0.13-mum CMOS technology with low-swing signaling, one of the proposed codes provides 2.14times speedup and 27.5% energy savings at the cost of 2.1times area overhead, but without any loss in reliability

Coding for systern-on-chip networks: a unified framework

Global buses in deep-submicron (DSM) system-on-chip designs consume significant amounts of power, have large propagation delays, and are susceptible to errors due to DSM noise. Coding schemes exist that tackle these problems individually. In this paper, we present a coding framework derived from a communication-theoretic view of a DSM bus to jointly address power, delay, and reliability. In this framework, the data is first passed through a nonlinear source coder that reduces self and coupling transition activity and imposes a constraint on the peak coupling transitions on the bus. Next, a linear error control coder adds redundancy to enable error detection and correction. The framework is employed to efficiently combine existing codes and to derive novel codes that span a wide range of tradeoffs between bus delay, codec latency, power, area, and reliability. Using simulation results in 0.13-/spl mu/m CMOS technology, we show that coding is a better alternative to repeater insertion for delay reduction as it reduces power dissipation at the same time. For a 10-mm 4-bit bus, we show that a bus employing the proposed codes achieves up to 2.17/spl times/ speed-up and 33% energy savings over a bus employing Hamming code. For a 10-mm 32-bit bus, we show that 1.7/spl times/ speed-up and 27% reduction in energy are achievable over an uncoded bus by employing low-swing signaling without any loss in reliability.

Microwatt Embedded Processor Platform for Medical System-on-Chip Applications

Battery life specifications drive the power consumption requirements of integrated circuits in implantable, wearable, and portable medical devices. In this paper, we present an embedded processor platform chip using an ARM Cortex-M3 suitable for mapping medical applications requiring microwatt power consumption. Ultra-low-power operation is achieved via 0.5-1.0 V operation, a 28 fW/bit fully differential subthreshold 6T SRAM, a 90%-efficient DC-DC converter, and a 100-nJ fast Fourier transform (FFT) accelerator to reduce processor workload. Using a combination of novel circuit design, system architecture, and SoC implementation, the first sub-microwatt per channel electroencephalograph (EEG) seizure detection is demonstrated.

Coding for reliable on-chip buses: fundamental limits and practical codes

A reliable high-speed bus employing low-swing signaling can be designed by encoding the bus to prevent crosstalk and provide error correction. In this paper, we present fundamental limits on the number of wires required to achieve joint crosstalk avoidance and error correction in on-chip buses. We propose a code construction that results in practical encoding and decoding schemes with the number of wires being within 35% of the fundamental limits. The proposed codes, when applied to a 10-mm 32-bit bus in a 0.13-/spl mu/ CMOS technology with low-swing signaling, provide 2.14/spl times/ speed-up and 27.5% energy savings without any loss in reliability.

Joint Equalization and Coding for On-Chip Bus Communication

In this paper, we propose using joint equalization and coding to improve on-chip communication speeds by signaling at rates beyond the rate governed by resistance-capacitance (RC) delay of the interconnect. Operating beyond the RC limit introduces inter-symbol interference (ISI). We mitigate the effects of ISI by employing equalization. The proposed equalizer employs a variable threshold inverter whose switching threshold is modified as a function of past output of the bus. We demonstrate even higher speedups by combining equalization with crosstalk avoidance coding. Specifically, simulation results for a 10-mm 32-bit bus in 0.13-mum CMOS technology show that 1.28 speedup is achievable by equalization alone and 2.30 speedup is achievable by joint equalization and coding.

Ultra-low power microcontrollers for portable, wearable, and implantable medical electronics

An aging population, coupled with choices on diet and lifestyle, is causing an increased demand for portable, wearable, and implantable medical devices that enable chronic disease management and wellness assessment. Battery life specifications drive the power consumption requirements of integrated circuits in these devices. Microcontrollers provide the right combination of programmability, cost, performance, and power consumption needed to realize such devices. In this paper, we describe microcontrollers that are enabling todays medical applications and discuss innovations necessary for enabling future applications with sophisticated signal processing needs. As an example, we present the design of an embedded microcontroller system-on-chip that achieves the first sub-microwatt per channel electroencephalograph (EEG) seizure detection.