Jay Maxey

Microwatt embedded processor platform for medical system-on-chip applications

A medical system-on-chip (SoC) that integrates an ARM Cortex-M3 processor is presented. Ultra-low power operation is achieved via 0.5–1.0 V operation, a 28 fW/bit fully differential subthreshold 6T SRAM, a 90%-efficient DC-DC converter, and a 100-nJ fast Fourier transform (FFT) accelerator to reduce processor workload. Using a combination of novel circuit design, system architecture, and SoC implementation, the first sub-microwatt per channel electroencephalograph (EEG) seizure detection is demonstrated.

Microwatt Embedded Processor Platform for Medical System-on-Chip Applications

Battery life specifications drive the power consumption requirements of integrated circuits in implantable, wearable, and portable medical devices. In this paper, we present an embedded processor platform chip using an ARM Cortex-M3 suitable for mapping medical applications requiring microwatt power consumption. Ultra-low-power operation is achieved via 0.5-1.0 V operation, a 28 fW/bit fully differential subthreshold 6T SRAM, a 90%-efficient DC-DC converter, and a 100-nJ fast Fourier transform (FFT) accelerator to reduce processor workload. Using a combination of novel circuit design, system architecture, and SoC implementation, the first sub-microwatt per channel electroencephalograph (EEG) seizure detection is demonstrated.

Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL

A self-biased PLL uses a sampled feed-forward filter network and a multi-stage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of multiplication factor, output frequency, and PVT. The PLL achieves a multiplication range of 1 to 4096 with < 3.8% period jitter at 1.5V supply. Fabricated in 0.13/spl mu/m CMOS, the area is 0.182mm/sup 2/ and the supply is 1.5V.

Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages

A method to minimize the supply sensitivity of a CMOS ring oscillator is proposed through joint biasing of the supply and the control voltage. The technique can supplement a number of common supply rejection techniques and can be exploited to compensate for the noise coupling caused by the parasitic capacitance in the loop filter of a phase-locked loop (PLL). The proposed CMOS ring oscillator is designed and implemented with a charge-pump based PLL in 65-nm technology to demonstrate the robustness against the supply fluctuation. Taking advantage of the negative static supply sensitivity of the ring oscillator with proper combination of the bias voltages, the rms jitter of the 5.12-GHz output clock is reduced from 6.41 ps to 2.38 ps while subject to supply noise at 90 MHz.

Minimizing the supply sensitivity of CMOS ring oscillator by jointly biasing the supply and control voltage

A method to minimize the supply sensitivity of a CMOS ring oscillator is proposed through joint biasing of the supply and the control voltage. The technique can supplement a number of common supply rejection techniques. The proposed CMOS ring oscillator is designed and implemented with a charge-pump based phase-locked loop in 65-nm technology to demonstrate the robustness against the supply fluctuation. Taking advantage of the negative static supply sensitivity of the ring oscillator with proper combination of the bias voltages, the rms jitter of the 4-GHz output clock is reduced from 10.66-ps to 5.04-ps while subject to switching noise with magnitude of 2.5% of the supply voltage at 150-MHz. Furthermore, more than 4.5times of reduction in the power consumption is achieved.

A nonlinear phase detector for digital phase locked loops

This paper examines several transfer curves of the phase detector in a digital phase-locked loop and illustrates the benefits of applying non-linearity to the phase transfer characteristics. Taking advantage of the programmability of the digital implementation, the proposed technique shows a better trade-off between the acquisition speed and the steady-state dithering jitter performance.