Srivatsan Chellappa

Methodology to optimize critical node separation in hardened flip-flops

Radiation hardening is a requirement for microelectronic circuits used in aerospace applications as they are prone to radiation induced upsets from high altitude neutrons and ions. The most common method to harden VLSI circuits is to use hardened flip-flops (FFs). The design of these FFs is made more difficult with increasing multi-node charge collection (MNCC) in advanced scaled fabrication processes, which requires that charge storage and other sensitive nodes be separated so that one impinging radiation particle does not affect redundant nodes simultaneously. In this paper we describe a correct by construction design methodology to determine a-priori which hardened FF nodes must be separated, as well as a general interleaving scheme to achieve this separation. We apply the methodology to radiation hardened flip-flops and demonstrate optimal circuit physical organization for protection against multi-node charge collection.

SRAM-Based Unique Chip Identifier Techniques

Integrated circuit (IC) identification using unclonable digital fingerprints facilitates the authentication of ICs, device tracking, and cryptographic functions. In this paper, we present two hardware methods exploiting the inherent process-induced mismatch of SRAM cells. The proposed circuits improve upon those previously published by reducing the number of bits that vary from trial to trial, and can be used at times other than just IC power-up. The proposed circuits and methods are compared with the previous power-up approach using the experimental results from a 90-nm test chip. The required SRAM array periphery circuit changes allow the use of standard foundry SRAM cells and do not impact the memory access time.

Design and Experimental Validation of Radiation Hardened by Design SRAM Cells

The design and electrical characterization of a total ionizing dose hardened by a design static random access memory (SRAM) cell using annular layout and guard rings are presented. Since foundry SRAM cells can be validated during process development and manufacturing ramp but radiation hardening by design cells cannot, we use a specialized test structure to validate the cell design here. Stability, manufacturability, and hardness are experimentally investigated using a 4 kbit SRAM structure, fabricated on one version of the foundry 90 nm process. The structure, combined with a novel test and simulation based extraction procedure, allows direct measurement of the as-fabricated cell electrical characteristics. Variation of the SRAM switching points due to irradiation as well as the individual transistor threshold voltage variability is measured in the SRAM array test structure. Irradiation tests show negligible impact on switching voltage and increase in the standby current less than 1.5% after 2 Mrad(Si). The effects on the cell margins are also analyzed. The specific SRAM cell layout, which uses a very low aspect ratio, is intended to minimize multibit upset of horizontally adjacent cells. This impact is also discussed with measured heavy ion results.

A 90-nm radiation hardened clock spine

A RHBD clock distribution network is described that reliably synchronizes the flow of signals through an integrated circuit in the presence of SETs. The clock spine design controls both redundant and non-redundant hardened circuits. The design uses techniques to reduce the jitter due to SETs, as well as error detection at every clock edge, since errors may be in the clock gating enables rather than the clocks themselves. The clock spine has been fabricated and tested on both standard and a low power 90-nm test chips, and proven hard as demonstrated by both heavy ion and proton broad beam testing.

In-situ characterization and extraction of SRAM variability

Measurement and extraction of as fabricated SRAM cell variability is essential to process improvement and robust design. This is challenging in practice, due to the complexity in the test procedure and requisite numerical analysis. This work proposes a new single-ended test procedure for SRAM cell write margin measurement. Moreover, an efficient decomposition method is developed to extract transistor threshold voltage (VTH) variations from the measurements, allowing accurate determination of SRAM cell stability. The entire approach is demonstrated in a 90 nm test chip with 32 K cells. The advantages of the proposed method include: (1) a single-ended SRAM test structure with no disturbance to SRAM operations; (2) a convenient test procedure that only requires quasi-static control of external voltages; and (3) a non-iterative method that extracts the VTH variation of each transistor from eight measurements. The new procedure enables accurate predictions of SRAM performance variability. As validated with 90 nm data of write margin and data retention voltage, the prediction error from extracted VTH variations is <; 4% at all corners.

Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation

Power dissipation is a major concern in sub-nanometer IC designs with technology scaling pushing towards higher clock frequencies. Techniques such as dynamic voltage (and frequency) scaling (DVS) to minimize power while providing good throughput have become commonplace. This paper presents a fully pipelined 256-bit key advanced encryption system (AES) design implemented with power-saving pulse-clocked latches as pipeline flip-flops that supports pipeline collapse, whereby pipeline stages can be unified by making stage latches transparent. The design is fabricated on a foundry 90-nm low standby power process. Measured results show the design is capable of 64 Gb/s encryption, limited by the I/O speed. A 7.6% decrease in the energy per operation beyond DVS power reduction using pipeline stage unification (PSU) is obtained.

Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU

Hardening the flip-flops and latches is the most straightforward way to improve the soft-error robustness of sequential logic circuits. This paper presents novel pulse-clocked latch based flip-flops that mitigate not just single event upsets (SEUs) but also single event transients (SETs) that are an increasing threat in high performance logic. The design uses triple-mode redundant latches, combined with appropriate clocking to provide redundancy in both space and time. Analysis of the flip-flop operation and immunity to both SEUs and SETs, as well as layout that provides adequate critical node separation to prevent multi-node charge collection failures, are presented. The multi-bit flip-flop macro has been fabricated and tested functional as shift registers on a 90-nm foundry LP process.

A soft-error hardened process portable embedded microprocessor

An embedded microprocessor core designed to have high soft-error immunity is presented. The design achieves hardness via architectural, micro-architectural, and circuit techniques. The basis of the machine is a dual-redundant speculative pipeline that detects mismatches at their commission to architectural state. Added instructions allow software controlled recovery and restart of upset instructions. Key architectural state is stored in triple-mode redundant, self-correcting logic. Special automated place and route flows afford robustness against multiple node charge collection. Full clock gating allows low power, while redundant clocks mitigate clock upset induced errors. Register file based caches allow near-threshold low voltage operation. The design is implemented on a commercial 90-nm bulk CMOS process. Silicon results, including error correction examples, are presented.

Physical design methodologies for soft error mitigation using redundancy

This paper demonstrates methodologies for designing soft-error hardened logic on commercial foundry processes. Physical design flows employ standard CAD tools to provide spatial separation that alleviates risk of multiple node charge collection upsets. To demonstrate and compare the proposed techniques, an advanced encryption standard (AES) encryption engine is implemented with the proposed methodologies. The methodologies incur an area overhead of 3.4× for a self-correcting, transient immune TMR design and 1.6× for a design using TMR flip-flops with non-redundant logic providing only single-event upset mitigation, over a non-redundant design. Power dissipation increases to 4.82× and 2.4×, respectively.

Architectural and Micro-Architectural Techniques for Software Controlled Microprocessor Soft-Error Mitigation

A MIPS 4Kc compliant embedded microprocessor core design that incorporates architectural features for software controlled radiation upset recovery is presented. The design uses fault tolerance techniques, i.e., error detection and instruction restart, implemented at the micro-architectural level, with architectural level changes, i.e., new instructions, for error recovery. Fine-grained, self-correcting triple mode redundant circuits protect key architectural state, in addition to dual mode redundancy in the instruction execution pipelines, cache subsystems, and error detection and correction in the register file. The design is implemented in a commercial low standby power 90-nm bulk low standby power CMOS process and the prototype operates at up to 336 MHz.