Vinay Vashishtha

ASAP7: A 7-nm finFET predictive process design kit

Abstract We describe a 7-nm predictive process design kit (PDK) called the ASAP7 PDK, developed in collaboration with ARM Ltd. for academic use. The PDK is realistic, based on current assumptions for the 7-nm technology node, but is not tied to any specific foundry. The initial version assumes EUV lithography for key layers, a decision based on its present near cost-effectiveness and resulting simpler layout rules. Non-EUV layers assume appropriate multiple patterning schemes, i.e., self-aligned quadruple patterning (SAQP), self-aligned double patterning (SADP) or litho-etch litho-etch (LELE), based on 193-nm optical immersion lithography. The specific design rule derivation is explained for key layers at the front end of line (FEOL), middle of line (MOL), and back end of line (BEOL) of the predictive process modeled. The MOL and BEOL DRC rules rely on estimation of time dependent dielectric breakdown requirements using layer alignments determined with projected machine to machine overlay assumptions, with significant guard-bands where possible. A high density, low-power standard cell architecture, developed using design/technology co-optimization (DTCO), as well as example SRAM cells are shown. The PDK transistor electrical assumptions are also explained, as are the FEOL design rules, and the models include basic design corners. The transistor models support four threshold voltage (Vth) levels for both NMOS and PMOS transistors. Cadence Virtuoso technology files and associated schematic and layout editing, as well as netlisting are supported. DRC, LVS, and full parasitic extraction is enabled through Mentor Calibre decks.

Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit

This paper discusses the back-end-of-line (BEOL) layers for a 7 nm predictive process design kit (PDK). The rationale behind choosing a particular lithographic process—EUV lithography, self-aligned double patterning (SADP), and litho-etch litho-etch (LELE)—for different layers, in addition to some design rule values, is described. The rules are based on the literature and on design technology co-optimization (DTCO) evaluation of standard cell based designs and automated place-and-route experiments. Decomposition criteria and design rules to ensure conflict-free coloring of SADP metal topologies and manufacturable SADP photolithography masks are discussed in detail. Their efficacy is demonstrated through successful coloring and photolithography mask derivation for target metal shape layouts, which represent corner cases, by using the Mentor Graphics Calibre and multi-patterning tools. Edge placement errors, misalignment, and critical dimension uniformity are included in the analysis.

Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation

Power dissipation is a major concern in sub-nanometer IC designs with technology scaling pushing towards higher clock frequencies. Techniques such as dynamic voltage (and frequency) scaling (DVS) to minimize power while providing good throughput have become commonplace. This paper presents a fully pipelined 256-bit key advanced encryption system (AES) design implemented with power-saving pulse-clocked latches as pipeline flip-flops that supports pipeline collapse, whereby pipeline stages can be unified by making stage latches transparent. The design is fabricated on a foundry 90-nm low standby power process. Measured results show the design is capable of 64 Gb/s encryption, limited by the I/O speed. A 7.6% decrease in the energy per operation beyond DVS power reduction using pipeline stage unification (PSU) is obtained.

Robust 7-nm SRAM design on a predictive PDK

SRAMs are ubiquitous in modern VLSI design but have become difficult to design in advanced finFET processes due to fin quantization and large variability at small geometries. In this paper six transistor SRAM design on a 7-nm predictive PDK is presented. The SRAMs use differential sense amplifier based sensing to support long bit-lines and high array efficiency. Different SRAM cells are evaluated statistically, resulting in the choice of a 122 cell due to its easier lithography and superior write margins. A novel switched capacitor reduced column VDD is presented, which has excellent across corner voltage characteristics and speed. The analysis shows yield to a minimum VDD of 500 mV.

Delay and power tradeoffs for static and dynamic register files

Register file (RF) memory is important in low power SOCs due to its inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic register files. In this paper, we compare static and dynamic RF power dissipation and timing characteristics. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height. One version, fabricated on a foundry bulk CMOS 90-nm low standby power (LP) process provides a baseline for the analyses.

Systematic analysis of the timing and power impact of pure lines and cuts routing for multiple patterning

Line and cut based patterning for BEOL layers is an attractive solution to address the block mask patterning challenges related to self-aligned double patterning. It also enables integrated fill, with fill as an artifact of unused metal routes following lines and cuts patterning. Traditional post-layout fill involves inserting metal at large distances to limit design impact, but is less effective at alleviating metal thickness variation due to density effects. While integrated fill reduces metal thickness variation, it has a negative impact on capacitance, delay and power dissipation. This work studies the impact of pure lines/cuts integrated fill on design performance metrics using a predictive 7 nm PDK. Two fully implemented auto-place and routed (APR) designs are considered for the experiments, one small and one large. Our comparison is from no fill to integrated fill, assuming conventional fill would not impact timing. The impact of integrated fill on capacitance and overall timing is evaluated using Calibre PEX and PrimeTime. We show these results are in line with simple “back of the envelope” estimates and simple models and are very significant for large designs.

A soft-error hardened process portable embedded microprocessor

An embedded microprocessor core designed to have high soft-error immunity is presented. The design achieves hardness via architectural, micro-architectural, and circuit techniques. The basis of the machine is a dual-redundant speculative pipeline that detects mismatches at their commission to architectural state. Added instructions allow software controlled recovery and restart of upset instructions. Key architectural state is stored in triple-mode redundant, self-correcting logic. Special automated place and route flows afford robustness against multiple node charge collection. Full clock gating allows low power, while redundant clocks mitigate clock upset induced errors. Register file based caches allow near-threshold low voltage operation. The design is implemented on a commercial 90-nm bulk CMOS process. Silicon results, including error correction examples, are presented.

Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit

Educators and researchers exploring integrated circuit design methods need models and design flows for advanced integrated circuit processes. As commercial processes have become highly proprietary, predictive technology models fill the gap. This work describes a design flow for ASAP7, the first 7 nm FinFET PDK, including schematic and layout entry, library characterization, synthesis, placement and routing, parasitic extraction, and HSPICE simulation.

ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper

This work discusses the ASAP7 predictive process design kit (PDK) and associated standard cell library. The necessity for multi-patterning (MP) techniques at advanced nodes results in the standard cell and SRAM architecture becoming entangled with design rules, mandating design-technology co-optimization (DTCO). This paper discusses the DTCO process involving standard cell physical design. An assumption of extreme ultraviolet (EUV) lithography availability in the PDK allows bi-directional M1 geometries that are difficult with MP. Routing and power distribution schemes for self-aligned quadruple patterning (SAQP) friendly, high density standard cell based blocks are shown. Restrictive design rules are required and supported by the automated place and route (APR) setup. Supporting sub-20 nm dimensions with academic tool licenses is described. The APR (QRC techfile) extraction shows high correlation with the Calibre extraction deck. Finally, use of the PDK for academic coursework and research is discussed.

A Soft-Error Mitigated Microprocessor With Software Controlled Error Reporting and Recovery

A MIPS 4Kc compliant embedded microprocessor design that incorporates architectural features for software controlled soft-error recovery is presented. The design leverages classical fault tolerance techniques, e.g., error detection and instruction restart, implemented at the micro-architectural level, and added instructions for error recovery. Soft-errors are detected as the instructions commit to architectural state. At this point, an exception is taken and software recovers the correct machine state and restarts execution. The software recovery allows full machine inspection to determine error root causes. Added instructions also facilitate silicon validation of the hardware and software recovery mechanisms. The design is implemented in a commercial low standby power 90-nm bulk CMOS process and the prototype operates at up to 336 MHz. Finally, proton broad beam irradiation results are presented. The processor demonstrates correct recovery, resuming program operation, from over 500 detected soft-errors, with no unrecoverable errors.