Stefan Härter

Computed-Tomography-Based Analysis of Voids in SnBi57Ag1 Solder Joints and Their Influence on the Reliability

The first area of research in this article focuses on the characterization of solder joints that contain voids by means of computed tomography (CT). This non-destructive test method made it possible to detect both cracks and voids in solder joints, to define their precise positions, and to capture the void volume of each void. In addition to CT, we carried out metallographic examinations so that we could demonstrate the interaction of both methods. In the process, CT was used to localize the defect and metallography to display the defect in high resolution. The article goes on to discuss the question of whether voids have an effect on the thermo-mechanical reliability of SnBi57Ag1 solder joints. For this purpose, the solder joints were first classified by their void area ratio using radioscopy. In order to analyze the effect of the void area ratio on the reliability of the joint, the assembly underwent an accelerated aging process through thermal shock testing according to IPC 9701. Subsequently, the shocked assemblies were sheared. With the shear values after 1000 cycles, we were able to show that the voids affect the reliability of the SnBi57Ag1 solder joints only slightly and that the joints were hardly damaged. By means of CT examinations performed prior to the thermal shocks, cracks starting from the meniscus tip could be attributed to the temperature changes. These cracks may be crucial when they occur with cracks found on macrovoids inside the meniscus.

Processing and reliability analysis of flip-chips with solder bumps down to 30 μm diameter

The accelerated trend to smaller and lighter electronics has accentuated many efforts towards size reduction and increased performance in electronic products. However, equipment and processes of electronics production have to come along with this trend when it comes to connections on board level. The use of flip-chip bonding technology employing micro bumps for very fine pitch packaging is becoming increasingly important in the microelectronics industry. To meet these requirements, cost-efficient solder bumping and automated assembly technologies for the processing of flip-chips have been developed and qualified. Flip-chips used in this study show a pitch of 100 μm and solder ball diameter of 40 μm and 30 μm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer (WLSST) process and solder sphere jetting (SB²) technology, respectively. The latter is a technique that has been used for many years in the wafer level packaging industry and is commonly known as a solder ball bumping tool. For the described work the SB² technology was scaled down for processing solder spheres with diameters of 30 μm with very good results achieved. Our research has shown that the underfill process is one of the most crucial factors when it comes to flip-chip miniaturization for high reliability applications. Therefore, a total of thirty different underfill materials were investigated initially in terms of flow time, gap height, filler sedimentation, and reliability. For reliability investigations, various standardized test conditions were applied to the test specimen. In previous experiments we found out that solder spheres of 50 μm seem to be the technological limit with current organic printed circuit board technology with subtractive structuring. Therefore, thin film ceramic as substrate material has been used showing excellent performance of the highly miniaturized solder joints at several reliability tests. Concluding long-term reliability and an analysis of the intermetallic growth are shown using SEM/EDX. Additionally, an analysis of the failure mechanism will be presented and recommendations for further miniaturization will be outlined. Advantages of the developed technology are lower cost compared to known techniques, very high flexibility and freedom in selection of solder composition including SAC, low melting alloys, gold-tin, and further special alloys.

Reliability study of lead-free flip-chips with solder bumps down to 30 μm diameter

The ongoing trend to miniaturized electronics has induced many developments towards size reduction and increasing performance in electronic products. To meet these requirements the involved processes, materials and components in electronics production have to be enhanced for high performance and high reliability. Flip-chip technology is one technology of choice with potential for highest integration. In previous investigations technologies for cost-efficient solder bumping and automated assembly in an industrial environment were evaluated. Wafer level solder sphere transfer and solder sphere jetting were adapted to provide flipchips with solder bump diameters down to 30 μm for flip-chip assembly onto printed circuit boards as well as onto thin film ceramic substrates. The reliability tests done so far showed excellent achievable reliability performance of these ultrafine-pitch assemblies under various test conditions. Since electromigration of flip-chip interconnects is a very important reliability concern, characterization of new interconnect developments needs to be done regarding the electromigration performance in accelerated life tests. For all experiments, specially designed flip-chips with 10 mm by 10 mm by 0.8 mm in size have been used. The silicon die layout provides a pitch of 100 μm with solder bump sizes between 60 μm and 30 μm in diameter. The solder spheres consist of lead-free SnAgCu alloy and are placed on a Ni-P under bump metallization which has been realized in an electroless nickel process. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements with separate daisy chain connections for each test coupon provide exact lifetime data during the electromigration tests, which are in some cases still in progress. Cross sectioning has been employed for the analysis of thermal diffusion as well as of the impact of electromigration influence on the failure mechanism using optical, SEM and EDX analysis, respectively. Reliability plots will be discussed regarding the electromigration performance for different test conditions applied to the respective test specimen for lifetime estimations.

Challenges of the Miniaturization in the Electronics Production on the example of 01005 Components

The electronics production experiences a continuous trend towards miniaturization of components. Smaller components lead to a number of challenges in the Surface Mount Technology (SMT) process chain to ensure a stable production process. This paper provides an overview on the main SMT production processes and focuses on the stencil printing process, which is said to be an error-prone process and has the demand of further optimization and research. One important criteria for the solder paste printing stencils is the area ratio (AR), which is defined by the IPC-7525 as the area of the aperture opening to the area of the aperture walls. Especially in mixed assembly designs AR is becoming critical low for the miniaturized 01005 components. In this paper, the printing process for miniaturized components is investigated using specially designed area ratio test stencils and an active squeegee system. The design of these stencils includes values for the AR from 0.65 down to 0.45 with different aperture shapes, which include gradually adjusted in length and width, rectangles as well as circular apertures for reference. Furthermore, the orientation of the rectangular apertures in relation to the printing direction is regarded. To include the effect of the active squeegee system all tests were conducted with the system activated as well as deactivated.