Stefan Joeres

A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25

Quadrature bandpass SigmaDelta modulators based on polyphase filters are suited for analog-to-digital conversion in GSM/EDGE low-IF receivers. This paper presents a continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulator with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology - which is a desirable solution for implementation in low power applications. A new compensation scheme for the polyphase filter is proposed. The summation of feedforward signals is implemented by weighted capacitors, without the necessity of any additional active components. The effectiveness of the proposed architecture is proved on a test chip which was designed in a standard 0.25 mum CMOS technology. The designed SigmaDelta modulator has a power consumption of 2.7 mW at 1.8 V supply voltage, a dynamic range of 90.3 dB and a peak SNDR of 86.8 dB. The chip area is 0.5 times 1.4 mm2 including pads.

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In this paper, starting from theoretical considerations on the chosen architecture, chip design and measurement results are presented for a continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulator for a combined GPS and Galileo low-IF receiver. The modulator chip was designed in a standard 0.25 mum CMOS technology. The designed CT quadrature bandpass SigmaDelta modulator has a power consumption of 20.5 mW with 1.8-V supply voltage, a dynamic range of 57.5 dB and 50.2 dB and a peak SNDR of 52.9 dB and 48.4 dB for GPS/Galileo, respectively. The core area of the chip is 0.37 times 0.54 mm2.

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The modeling language VerilogAMS supports a new double precision datatype (wreal) that enables analog accuracy in the digital simulation domain. It is therefore possible to separate high frequency signal paths, like those in RF frontends, from the rest of the chip, which comes in very handy for fast verification purposes. After an introduction to analog and digital modeling, a strategy to model the RF and LO signal flow path for a bluetooth transceiver system is presented. Especially the nonuniform oversampling, which is introduced through wreal to electrical and vice versa conversion, is analyzed and compared to traditional uniform sampling ratios. The proposed approach is demonstrated for an industrial available RF frontend, including biasing and analog to digital conversion. Simulation comparisons for different complexities of the frontend and different modeling approaches like passband, baseband and transistor level conclude the paper.

Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GPS/Galileo Low-If Receiver

The main focus of this work is the functional verification of radio frequency (RF) transceivers and RF systems on chip (SoCs). The use of enhanced baseband behavioral description models for an industrial available multiband, low IF GSM receiver is demonstrated. The necessity of functional verification when dealing with complex baseband signals and mixing operations with high/low sideband possibilities is shown. Future demands on language constructs and their implementations into the design flow are presented. Fundamental simulation comparisons for different implementation levels and proposals for new constructs to ensure functionality and connectivity between advanced behavioral description level and transistor schematics are made. This paper concludes with a suggestion for an extension of the Verilog-HDL-family to aid SoC designers in their effort to shorten the time to market and demonstrates the possible benefits of upcoming systemVerilog constructs

Event driven analog modeling of RF frontends

Since the design and realization of a complex system on a chip is error prone, functional verification should have been a main task in todays design flows but is still underestimated. This paper gives an overview of current modeling approaches to handle functional verification of a design on the top level, prior to tape out. The problems that arise from the different approaches such as baseband modeling and event-driven modeling are explained, and the resulting effects on the simulated system specifications are presented. The necessity of the approaches for future systems, which are not simulatable with current methods, is presented, and the needed extensions of the hardware description languages and simulators are proposed.

Functional Verification of Radio Frequency SoCs using Mixed-Mode and Mixed-Domain Simulations

This paper presents a strategy for successful polyphase-filter design for continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulators. Based on a low-pass filter with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology - which is suited for implementation in low-power applications - analytical equations are derived. A new compensation scheme is proposed and implemented by cross-coupling additional resistors, without the necessity of extra-active components. Translation to intermediate frequency in second- and fourth-order polyphase filters with the proposed compensation scheme are compared to analytical considerations and simulation. Nonlinearities introduced by mismatch of feedforward coefficients and finite gain-bandwidth of amplifiers are considered.

Modeling Approaches for Functional Verification of RF-SoCs: Limits and Future Requirements

This paper describes an extension to the popular Matlab delta-sigma toolbox. The delta-sigma toolbox is restricted to the generation and simulation of low-pass DeltaSigma analog to digital converters (ADCs). This work enables the toolbox to generate and simulate quadrature bandpass (polyphase) ADCs. After a short introduction and general explanations of DeltaSigma based ADCs, the generation of optimized polyphase loop filters from their lowpass equivalents using the toolbox approach is described. The corresponding sourcecodes for generation and simulations of these ADCs are provided. Demonstration examples with various simulation results are supplied. The toolbox enhancements have been published for download at the Mathworks Matlab internet site.

A Polyphase Filter Design for Continuous-Time Quadrature Bandpass Sigma–Delta Modulators

Continuous-time (CT) SigmaDelta modulators seriously suffer from excess loop delay, which can not be seen in discrete-time designs. In this paper, it is shown that excess loop delay decreases the signal-to-noise ratio (SNR), input dynamic range (DR) and stability in CT complex SigmaDelta modulator with CIFF topology. A method for its compensation is presented. The proposed compensation scheme has a unity delay in front of the quantizer and complex compensation coefficients which are determined by analysis of the ideal DT loop filter transfer function. The simulation results are compared to analytical considerations.

Simulation of quadrature-bandpass Sigma-Delta analog to digital converters using state space descriptions

The functional verification of radio frequency circuits is the main target of this work. The use of baseband behavioral description models for Bluetooth/spl trade/ and WLAN receivers is demonstrated. Fundamental simulation comparisons for different implementation levels are made. This paper concludes with a suggestion for an extension of the Verilog-HDL-family to aid SoC designers in their desire to shorten the time to market.

A compensation method of the excess loop delay in continuous-time complex sigma-delta modulators

This paper presents a continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulator with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology-which is suited for implementation in low power applications. A new compensation scheme for a polyphase filter is proposed. The summation of feedforward signals is implemented by weighted capacitors, without the necessity of any additional active components. The effectiveness of the proposed architecture is proved on a test chip which was designed in a standard 0.25-mum CMOS technology. The designed SigmaDelta modulator has a power consumption of 2.7 mW at 1.8 V supply voltage, a dynamic range of 90.3 dB and a SNDR of 86.8 dB. The chip is 0.5 times 1.4 mm2 including pads.