Stefan Mollov

A Soft-Switched Asymmetric Flying-Capacitor Boost Converter With Synchronous Rectification

The multilevel flying-capacitor boost converter was analyzed for asymmetric voltage operation-this permits loss optimization that takes advantage of different voltage class MOSFETs. A cost-motivated design of a suitable zero-voltage zero-current switching snubber is then developed that permits a great reduction of the inductor size. With the proposed snubber, synchronous rectification operation is compared to that of diode boost, with a particular attention to the contribution of nonlinear MOSFET parasitics. Experimental results from a 2-kW/30-kHz prototype justify the effectiveness of this solution with a conversion efficiency around 99% ± 0.1% for a wide load range.

Silicon carbide power chip on chip module based on embedded die technology with paralleled dies

A new three dimensional package based on Printed Circuit Board (PCB) embedded die technology is presented in this paper. The package takes advantage of the Power Chip On Chip (PCOC) concept, where commutation cell is housed within the bus bar, allowing a very low inductance design for the package of up to 0.25 nH. Two key design challenges with the package relate to the layout and the thermal management. Thus, a parallelization technique enabling impedance balancing is developed for the layout and validated using four parallel Silicon Carbide (SiC) MOSFETs. Gate circuit is carefully designed allowing low inductive behavior and low electromagnetic coupling. Finally, the thermal management of the module is studied and die attach with direct copper filled vias is validated.

Online junction temperature measurements for power cycling power modules with high switching frequencies

Traditionally, power cycling employs only electromechanical induced stress due to the heating caused by the conduction losses of a power device. Hence, potential failure modes caused by high dv/dt or the effects of temperature positive feedback of switching losses present under the actual application are not expressed in classical tests. In addition, traditional power cycling methods use temperature sensitive electrical parameters (TSEP), which are typically impractical to apply to pulse-width modulated power cycling tests that better represent the application conditions. Thus, this paper investigates online junction temperature measurement techniques and stress application strategies for a pulse-width modulated (PWM) based power cycling test bed used to age power module under near application conditions.

Comparison of planar and Toroidal PCB integrated inductors for a multi-cellular 3.3 kW PFC

The Printed-Circuit-Board (PCB) technology is attractive for power electronic systems as it offers a low manufacturing cost for mass production. In this paper, we present a procedure to design power inductors based on PCB. These inductors either use PCB for the winding only (Planar structure), or to host both the magnetic core and the winding (Toroidal PCB structure). The design procedure compares, in the form of a Pareto fronts, the two inductor structures over a large range of parameters (geometric parameters, magnetic materials), to identify the best candidates in terms of power losses and box volume. In this procedure, the core losses are taken into account using improved Generalized Steinmetz Equation (iGSE). The skin and proximity effects are considered using the AC resistance calculated with a FEM software. The inductor feasibility is checked from a mechanical perspective using the PCB design rules and from a thermal point of view with FEM simulation. A design case is presented for a 3.3 kW multi-cellular (3 interleaved cells) Power Factor Corrector (PFC). It is found that the planar design offers the most compact solution, but might present challenges regarding thermal management. The Toroidal PCB structure tends to be larger, but easier to cool.

Optimized power modules for silicon carbide MOSFET

An Integrated Power Board technology was used to construct a 3D power module. This packaging is suitable for use of WBG devices as it reduces the inductive parasitics to the strict minimum, with a 2nH loop inductance in our 1.2kV/80A SiC prototype using SiC MOSFETs. The packaging presents virtually no parasitics or necessity for slowing down the commutation, which is oscillation-free. The conducted emissions of the 3D module are more than halved in comparison to those of a bespoke wire-bonded, EMI-optimised module.

Improving the die utilization and lifetime in a multi-die SiC power module by means of integrated per-die gate buffers

The full utilization of the active devices within a SiC power module can be limited by the common stray inductive path imposed by the substrate layout. In this paper, the prospect of integrating individual gate bulfers per power die is explored for lowering the total losses of a power module, while maintaining a good thermal distribution across the set of dies. Each die within the power module has an increased utilization due not only having lowered losses, but due to the similar source inductive path for die, similar thermal loading. Using a 50kVA, 1.2kV, 8-die prototype power module, the overall switching losses using per-die bulfers is found to be reduced by a factor of 25%, while significantly improving the thermal distribution from die to die.

Lifetime extension of a multi-die SiC power module using selective gate driving with temperature feedforward compensation

Owing to the high current density but smaller die area of SiC components, high current SiC power modules typically feature a large number of parallel connected dies. Due to the faster electrical dynamics of these power modules, and the inherent mismatch of properties between the dies, certain dies can be poorly utilized — requiring either more dies to achieve a given current rating or a de-rating of the current handling capability of that module. This paper investigates the use of integrated per-die buffers with selective gate driving to minimize the thermal differences within a high current SiC power module. The predetermined selective gate driving pattern is based on the steady-state temperature distribution of the power module, and hence is used as a feed-forward term to compensate the thermal unbalance. The experimental results demonstrate a drop of 15°C in the hottest die using selective gate driving, corresponding to a lifetime increase of up to 3 times, according to the case study presented.

Multi-objective optimisation of a bidirectional single-phase grid connected AC/DC converter (PFC) with two different modulation principles

A design methodology is presented for a full-bridge Power Factor Corrector (PFC) converter with two control schemes: the well-known Continuous Current Mode (C.C.M) and Triangular Current Mode (T.C.M). The second one is an extension of the Discontinuous Current Mode (D.C.M). The converter is composed of one high frequency leg and one leg switching at the grid frequency and includes the EMC (common and differential mode) filter. This work highlights the impact of the modulation scheme on the design of passive components and on the overall losses. A pareto front in the efficiency (η) vs power density (ρ) domain is derived for both modulation schemes and for natural convection cooling. We show that, when EMC issues are considered, the T.C.M poses more constraints for partial load operation, superseding the full-load design. Finally, it is shown that for non-interleaved converters C.C.M modulation is better than T.C.M modulation, resulting in higher density converters.

Real-life vs. standard driving cycles and implications on EV power electronic reliability

This work studies the impact of drive cycles on the power semiconductor temperature, and consequently on the reliability figures. The paper quantifies the reliability errors stemming from the use of standard mission profiles by comparing them to data sets using real-life high-resolution mission profiles. It is found that standard drive cycles underestimate the stress on the power semiconductors. The paper thus proposes a new and more realistic Drive Cycle for Reliability Assessment (DCRA) to be used for lifetime estimation of power electronic components.