W. Stefanutti

Autotuning of Digitally Controlled DC–DC Converters Based on Relay Feedback

This paper proposes a simple autotuning technique for digitally controlled dc-dc converters. The proposed approach is based on the relay feedback method and introduces perturbations on the output voltage during converter soft-start. By using an iterative procedure, the tuning of proportional-integral-derivative parameters is obtained directly by including the controller in the relay feedback and by adjusting the controller parameters based on the specified phase margin and control loop bandwidth. A nice property of the proposed solution is that output voltage perturbations are introduced while maintaining the relay feedback control on the output voltage. The proposed algorithm is simple, requires small tuning times, and it is compliant with the cost/complexity constraints of integrated digital integrated circuits. Simulation and experimental results of a synchronous buck converter and of a dc-dc boost converter confirm the effectiveness of the proposed solution

Autotuning of Digitally Controlled Buck Converters Based on Relay Feedback

This paper proposes a simple autotuning technique for digitally controlled dc-dc synchronous buck converters. The proposed approach is based on the relay feedback method and introduces perturbations on the output voltage during converter soft-start. By using an iterative procedure, the tuning of PID parameters is obtained directly by including the controller in the relay feedback and by adjusting the controller parameters based on the specified phase margin and control loop bandwidth. A nice property of the proposed solution is that output voltage perturbations are introduced while maintaining the closed-loop control of the digitally controlled converters. The proposed algorithm is simple, requires small tuning times and it is compliant with the cost/complexity constraint of integrated digital ICs. Experimental investigation has been performed using discrete components, implementing the digital control in a field programmable gate array (FPGA). Simulation and experimental results of a 1.5 V-5 A synchronous buck converter confirm the effectiveness of the proposed solution

Fully digital hysteresis modulation with switching-time prediction

This paper proposes a digital hysteresis-modulation technique based on switching-time prediction. Sampling controlled variables several times within a switching period, it ensures a dynamic performance comparable to that obtainable with analog hysteresis modulation. Compared to conventional digital hysteresis modulation, it avoids frequency jitter since it predicts switching transitions. Compared to hysteresis modulation based on the detection of the zero crossing of current errors, it avoids external analog circuits. Compared to pulsewidth-modulation (PWM) techniques, it ensures faster dynamic response. These advantages are obtained at the expense of increased signal-processing requirements and of control complexity. Switching-frequency stabilization and synchronization with an external clock can be obtained extending the techniques proposed for analog hysteresis modulations. The proposed predictive algorithm does not require knowledge of load parameters and only a rough estimation of the inductor value, which can be easily self-adjusted. The proposed solution is suited for high-performance current (or sliding-mode) control where the digital hardware has enough computational power to allow multiple samples within a switching period. The proposed modulation technique has been applied to a sliding-mode control of a single-phase uninterruptible power supply (UPS). Experimental results confirm the effectiveness of the proposed approach.

Simplified Model Reference-Based Autotuningfor Digitally Controlled SMPS

This paper presents a closed-loop self-tuning technique for digitally controlled dc-dc switched-mode power supplies (SMPS) based on proportional-integral-derivative (PID) regulators, which derives from the more general model reference autotuning techniques. After briefly discussing an open loop, model-reference based tuning technique, a closed-loop solution is presented in which a perturbation frequency generated digitally is injected into the control loop and superimposed to the duty cycle command. The tuning is performed elaborating the signals right before and right after the injection point, and adjusting the PID parameters until predefined bandwidth and phase margin targets are obtained. The proposed approach allows for a robust and repeatable tuning, mainly because of the high resolution and dynamics available at the signal injection point. Moreover, the tuning is performed maintaining the closed-loop configuration, thus ensuring voltage regulation even during the PID adjustment, this being a fundamental constraint for most electronic equipments. The proposed technique is simple from the signal processing point of view, since it requires a few integrations, multiplications and phase-shift; further simplified implementations by employing nonsinusoidal perturbation waveforms like square-wave or triangular signals are also proposed. The approach is first discussed for two-parameters PI and PD regulators, and successively extended to PID structures, for which two possible implementations are proposed. The effectiveness of the tuning approach is verified by means of computer simulations and experimental tests carried out on a digital signal processor platform interfaced with a prototype point-of-load converter. The complexity of an HDL-implementation of the tuning hardware for field programmable gate array platforms is also discussed.

Analysis of Multi-Sampled Current Control for Active Filters

This paper investigates the multisampling techniques applied to the current control in active-power-filter (APF) applications. In APF applications with digital control, the main bandwidth limitation derives from A/D conversion and computational delays and the sampling-related delay of the digital pulsewidth modulation (DPWM). Using field-programmable gate arrays and fast A/D converters for the control implementation, it is possible to minimize the former two; thus, the overall phase lag is dominated by the DPWM, which can strongly be reduced by the multiple-sampling approach, breaking bandwidth limitations of single-sampled solutions. Moreover, as the multisampling approach triggers nonlinear behaviors that can negatively impact the filter-compensating capabilities, a solution based on a simple digital filter is proposed which linearizes the system behavior and does not waste the multisampling advantages. Simulation and experimental results on a 10-kVA prototype confirm the theoretical expectations.

Power Line Communication in Digitally Controlled DC–DC Converters Using Switching Frequency Modulation

This paper investigates power line communication (PLC) in digitally controlled high-frequency switched-mode power supplies in distributed architectures that share the same bus voltage. Communication between different DC-DC converters is obtained by using switching frequency modulation and by detecting the switching signal on the common supply bus voltage. In case of low power transmission, a small duty-cycle perturbation at half of switching frequency is added to enhance the energy of the transmitted signal. Each converter operates at three different switching frequencies: the first is associated with bit 1 transmission, the second is associated with bit 0 transmission, and the third is associated with no transmission state. In the proposed solution, there is no need for an additional power amplifier in order to inject the communication signal on the power lines, but the signal used for the PLC is inherently generated by the pulsewidth modulation of DC-DC converters. Even if aimed at a dedicated digital IC, the communication architecture has been implemented in field-programmable gate arrays. Simulation and experimental results on DC-DC synchronous buck converters confirm that the performance is achievable by the proposed PLC techniques.

Digital Control of Single-Phase Power Factor Preregulators Based on Current and Voltage Sensing at Switch Terminals

This paper proposes a fully digital control of boost power factor preregulators (PFPs) with input voltage estimation that is suitable for smart-power integration. The proposed solution features a minimum pin count by avoiding input voltage sensing for the generation of the internal current reference and by sensing the output voltage through the direct sampling of the voltage across the power switch during its off interval at the line voltage peak. The control algorithm requires the estimation of the rectified input voltage, that is simply done by exploiting the integral part of the current loop proportional-integral regulator, and a phase-looked-loop (PLL) synchronization with the estimated line frequency for sampling the output voltage and rejecting the low-frequency output voltage ripple. The provisions needed to ensure correct output voltage sensing, even during transient and light-load conditions, are also discussed. Experimental results on a single-phase boost PFP show the properties of the proposed approach

Predictive Digital Control for Voltage Regulation Module Applications

A digital control technique for voltage regulation module (VRM) is investigated, which is based on a predictive current regulator. Due to the adaptive-voltage-positioning (AVP) of the VRM, the controlled variable includes a combination of output voltage and inductor current. Besides the predictive regulator, a disturbance observer is used for compensation of input voltage variations and any other source of errors, such as dead-times, parameter and model mismatches. Even if aimed to an integrated digital controller, experimental investigation has been performed using discrete components, implementing the digital control in a field programmable gate array (FPGA). Experimental results on a synchronous buck DC-DC converter confirm the properties of the predictive control

Simplified Model Reference Tuning of PID Regulators of Digitally Controlled DC-DC Converters Based on Crossover Frequency Analysis

An autotuning technique of voltage-mode regulators for digitally controlled dc-dc converters, which is based on model reference approach, is proposed. The system is excited by a frequency component which equals the desired control bandwidth. The difference between the output of real system and the one of the reference model is used to set regulator parameters in order to obtain desired gain and phase margin at the crossover frequency. The procedure is firstly described for two-parameters controllers (proportional-integral (PI) or proportional derivative (PD) controller) and then extended to more general PID regulators. The latter is obtained either injecting an additional frequency component, or, alternatively, using a single frequency signal in a two step procedure. The proposed solution has the advantage of simplicity, good precision in presence of sampling noise, independence on the converter topology, and small signal processing requirement. Experimental investigation has been performed on a synchronous buck converter, and both simulation and experimental results confirm the effectiveness of the proposed solution.

Prediction of limit-cycles oscillations in digitally controlled DC-DC converters using statistical approach

Digitally controlled DC-DC converters are affected by quantization effects on A/D converters and digital pulse-width modulators (DPWMs) which may result in undesirable limit-cycle oscillations. Existing static and dynamic models predict the existence of only a small part of limit cycle oscillations, so that extensive time-domain simulations are usually needed in order to verify the presence of limit-cycle oscillations under different load and input voltage conditions. This paper proposes an alternative approach based on statistical models. Modelling the quantization error as a white noise, including the quantization effects on the controller and converter state variables, and evaluating the correlation between state variables, a statistical prediction of limit-cycle oscillations is obtained. By means of the proposed method, design criteria for the regulator parameters, in terms of achievable bandwidth, location of PID zeros and desired phase margin, can be derived. Simulation and experimental results confirm the validity of the proposed method.