Stephan Eggersglüß

PASSAT 2.0: A multi-functional SAT-based testing framework

An important step in the manufacturing process is the postproduction test. Here, a test set is applied to each manufactured chip in order to detect defective devices. The test set is typically generated by ATPG (Automatic Test Pattern Generation) algorithms. Classical ATPG algorithms work on a gate-level netlist and use structural knowledge and heuristics to guide the search in order to obtain a test set. Additionally, the use of ATPG is coupled or accompanied by other test techniques to increase the quality and the compaction of the test set. For example, timing-aware ATPG integrates timing information into the search process to guide the heuristic towards determining the longest paths and n-detection test generation is used to increase the detection quality for unmodeled defects. Fault simulation is applied as a post-processing technique to remove detected faults from the fault list and, by this, to decrease the pattern count as well as the overall ATPG run time. Static and dynamic test compaction techniques are further used for test set compaction. All these techniques are well developed. However, solving them separately limits the quality of the results.

ATPG Based on Boolean Satisfiability

The first SAT-based ATPG approaches were proposed in the 1990s. However, these approaches did not become widely accepted because of some disadvantages such as the overhead for CNF transformation, missing support of multiple-valued logics and overspecified solutions. Additionally, existing structural ATPG algorithms were fast enough to cope with designs of that time.

Compact test set generation for test compression-based designs

The manufacturing test is an important and expensive part of the overall electronic design flow. A main cost factor is the steadily increasing test data volume. Modern designs typically use extra hardware, i.e. test compression hardware, to compress the scan patterns to save test data volume. However, this imposes constraints on the pattern generation process. A high number of unspecified bits is typically needed to compress a test pattern successfully. In this paper, a compact test set generation technique is proposed for test compression-based designs. The proposed technique is based on a fully-specified test set and uses test vector decomposition, multiple-fault-detection and atomic vector ordering in order to build a highly compact test set with a guaranteed percentage of unspecified bits. Experimental results on benchmark and industrial circuits show that the approach is able to achieve a significant pattern reduction compared to previous approaches. Furthermore, it is shown that a higher compaction of the basis test set leads to a higher compaction of the resulting partially-specified test set.

Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression

We present a formal optimization technique that enables retargeting for codeword-based IEEE 1149.1-compliant TAP controllers. The proposed method addresses the problem of high test data volume and Test Application Time (TAT) for a system-on-chip design during board or in-field testing, as well as during debugging. This procedure determines an optimal set of codewords with respect to given hardware constraints, e.g., embedded dictionary size and the interface to the Test Data Register in the IEEe 1149.1 Std. A complete traversal of the spanned search space is possible through the use of formal methods. An optimal set of codewords can be determined, which is directly utilized for retargeting. The proposed method is evaluated using test data with high-entropy, which is known to be the least amenable to compression, as well as input data for debugging and Functional Verification (FV) test data. Our results show a compression ratio improvement of more than 30% and a reduction in TAT up to 20% compared to previous techniques.

Test digitaler Schaltkreise

Eingebettete Systeme ubernehmen zentrale Steueraufgaben im taglichen Leben. In der Energieversorgung oder im Transportwesen wurde ein Ausfall der Systeme fatale Auswirkungen haben. Der Nutzer verlasst sich aber auf ein fehlerfreies Funktionieren des Systems. Die Funktionstuchtigkeit der Schaltkreise zu garantieren, ist das Ziel des Testens – und das mit geringen Kosten, da jeder Chip nach der Produktion separat getestet werden muss.

Automated formal verification of X propagation with respect to testability issues

X values may be captured by scan flipflops during the scan test. An X value corrupts the signature generated by a Multiple-Input Signature Register (MISR). The MISR is used in the test structures such as Logic Built-in Self-Test (LBIST). In this paper, we propose an approach to automate formal verification of X propagation with respect to testability issues. The propagation of an X value from X sources to scan flipflops is comprehensively evaluated using formal verification considering all possible test patterns. The approach is utilized to find root causes of a corrupted signature generated by MISR and to rectify the erroneous behavior of a design because of dangerous X sources.

An effective fault ordering heuristic for SAT-based dynamic test compaction techniques

Abstract Each chip is subjected to a post-production test after fabrication. A set of test patterns is applied to filter out defective devices. The size of this test set is an important issue. Generally, large test sets increase the test costs. Therefore, test compaction techniques are applied to obtain a compact test set. The effectiveness of these technique is significantly influenced by fault ordering. This paper describes how information about hard-to-detect faults can be extracted from an untestable identification phase and be used to develop a fault ordering technique which is able to reduce the pattern counts of highly compacted test sets generated by a SAT-based dynamic test compaction approach.

Circuits and Testing

This chapter gives the basic information about circuits and testing of circuits. The role of Automatic Test Pattern Generation (ATPG) in the production test is presented in Sect. 2.1. Section 2.2 gives information about the used abstraction level of circuits and shows the modeling as well as the basic notations for the circuit representation used. In Sect. 2.3, the meaning of a fault model is described and relevant fault models are introduced, while classical algorithms for test pattern generation for these fault models are presented in Sect. 2.4. Section 2.5 briefly reviews the industrial test environment.

Circuit-Based Dynamic Learning

The proportion of unclassified faults produced by today’s test generation algorithms grows due to the increased complexity of modern designs. However, a small percentage of unclassified faults is very important for the production test to keep a high fault coverage. Otherwise, faults may remain untested and defective devices could pass the test. A high fault coverage is needed to maintain a certain level of quality.

High Quality ATPG for Transition Faults

The Transition Fault Model (TFM) takes the prevalent position among the delay fault models in the industrial production test. This fault model is widely used to ensure that a manufactured circuit is free of delay defects. One major reason behind the widespread use of the TFM is the similarity to the SAFM. This allows for the application of existing ATPG algorithms, i.e. only one ATPG engine has to be maintained for both fault models. Furthermore, the TFM has a small fault population compared to the PDFM. The number of faults is linear in the number of gates. Designs which have a good stuck-at fault coverage typically also have a good transition fault coverage [WLRI87]. However, the growing complexity and size of today’s designs lead to a serious problem in industrial practice. Classical structural ATPG algorithms produce a large number of aborts and compromise the high fault coverage demands of the industry. The advantages of using SAT-based algorithms for test generation for the SAFM have already been shown in the previous chapters.