Mehdi Dehbashi

Automated Design Debugging in a Testbench-Based Verification Environment

Debugging is one of the major bottlenecks in the current VLSI design process as design size and complexity increase. Efficient automation of debugging procedures helps to reduce debugging time and to increase diagnosis accuracy. This work proposes an approach for automating the design debugging procedures by integrating SAT-based debugging with test bench based verification. The diagnosis accuracy increases by iterating debugging and counterexample generation, i.e., the total number of fault candidates decreases. The experimental results show that our approach is as accurate as exact formal debugging in 71% of the experiments.

On Modeling and Evaluation of Logic Circuits under Timing Variations

This paper presents a methodology to model and analyze the functional behavior of logic circuits under timing variations. In the framework, first a Time Accurate Model (TAM) of the circuit is constructed. The TAM represents the behavior of the circuit in the functional domain under a discrete time model. Afterwards, Variation Logic is inserted to apply the timing variations. Moreover, the circuit TAM is enhanced by Time Control (TC) logic to model the circuit frequency. We apply the proposed methodology to analyze a circuit or an approximate circuit under timing variations as well as to analyze a circuit under timing-induced errors for approximate computing.

Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs

As complexity and size of Systems-on-Chip (SoC) grow, debugging becomes a bottleneck for designing IC products. In this paper, we present an approach for online debug of NoC- based multiprocessor SoCs. Our approach utilizes monitors and filters implemented in hardware. Monitors and filters observe and filter transactions at run-time. They are connected to a Debug Unit (DU). Transaction-based programmable Finite State Machines (FSMs) in the DU check assertions online to validate the correct relation of transactions at run-time. The experimental results show efficiency and performance of our approach.

Debug Automation for Synchronization Bugs at RTL

One major concern in the design of Very-Large- Scale Integrated (VLSI) circuits is debugging as design size and complexity increase. Automation of the debugging process helps to decrease the development cycle of VLSI circuits and consequently to achieve a higher productivity. This paper presents an approach to automatically debug synchronization bugs due to coding mistakes at RTL. In particular, we introduce an appropriate bug model and show how synchronization bugs are differentiated from other types of bugs by our approach. The experimental results on LGsynth93 and ITC-99 benchmark suites and RTL modules of OpenRISC and OpenSPARC CPUs show diagnosis accuracy and efficiency of the approach.

Debug Automation for Logic Circuits Under Timing Variations

This paper presents a novel approach to automate speedpath debugging taking into account variations. The proposed technique is based on Boolean Satisfiability. The approach is based on converting the timing behavior of a circuit into the functional domain, inserting a variation logic into the model, and using a Boolean Satisfiability solver to extract failing speedpaths.

Sat-based speedpath debugging using waveforms

A major concern in the design of high performance VLSI circuits is speedpath debugging. This is due to the fact that timing variations induced by process variations and environmental effects are increasing as the size of VLSI circuits is shrinking. In this paper, a speedpath debugging approach based on Boolean Satisfiability (SAT) is proposed. The approach takes waveforms of the signals of a circuit into account. Waveforms and their propagation are encoded using SAT. Also, timing variation models for slowdown and speedup of each gate are incorporated into the model. The whole timing variation is controlled by a unit called variation control. Having an Erroneous Trace (ET) due to timing variation, our debug engine automatically finds potential failing speedpaths. The experimental results on ISCAS benchmarks show efficiency and diagnosis accuracy of our approach. The approach can also localize potential failing speedpaths for the multiplier circuit c6288 that has a large number of paths.

Functional analysis of circuits under timing variations

Summary form only given. This work proposes an approach to model and evaluate the functional behavior of logic circuits under timing variations. In the approach, first we construct a Time Accurate Model (TAM) of the circuit to represent its timing behavior in a functional domain under a discrete time model. Then, timing variations are applied by using Variation Logic (VL).

Automated Optimization of Scan Chain Structure for Test Compression-Based Designs

Test compression hardware blocks such as EDT 1 are utilized in large industrial designs to compress scan testdata in order to decrease scan test time and volume. Duringpattern generation for EDT-based designs, some faults cannotbe detected due to linear dependency and insufficient encodingcapacity of EDT. These faults called EDT Aborted (EAB) faultscause a notable coverage loss in some designs.In this work, a new approach is proposed to form scanchains such that the number of EAB faults decreases andthe test coverage increases. The approach places scan flipflopscorresponding to care bits at appropriate positions in orderto reduce linear dependency during pattern generation. Theapproach is totally automated and has been integrated into theexisting design flow. The experimental results on the industrialdesigns show that the new approach decreases the number of EAB faults significantly and achieves a high test coverage.

Analyzing Timing Variations

Variability is recognized to be a major challenge in analyzing the circuits as IC technology continues to scale down. In this case, delay deviations are imposed by process variations such as uncertainty in the parameters of fabricated devices and interconnects, and by environmental variations such as temperature and voltage [BCSS08, APP10, SGT+08].

Automated Debugging for Timing Variations

This chapter deals with the automation of post-silicon debugging for speed-limiting paths, briefly called speedpaths. Debugging of speedpaths is a key challenge in development of VLSI circuits as timing variations induced by process and environmental effects are increasing.