Stephan Kubisch

Dynamic reconfiguration with hardwired networks-on-chip on future FPGAs

Due to their layered approach, networks-on-chip (NoC) are a promising communication backbone in the field of heterogeneous dynamically reconfigurable systems. In this paper a future FPGA architecture is discussed having a hardwired NoC as an additional high-level routing resource. Instead of implementing on-chip interconnection with valuable reconfigurable resources, on top of this architecture, cost-efficient statically and dynamically reconfigurable systems can be built. The concept of such an FPGA is explored by means of an abstract SystemC model. This model not only implements the NoC but also permits a tile based dynamic reconfiguration. It is shown, that this approach advances the research on operating system support for dynamic reconfiguration in a new way.

A distributed object system approach for dynamic reconfiguration

Managing reconfigurable hardware resources at runtime is expected to be a new task for future operating systems. But due to the mixture of parallel and sequential parts of dynamically reconfigurable applications, it is not entirely clear so far, how to use and to program such systems. A new interpretation of dynamically reconfigurable applications is presented. It is shown, that the parallel computing concept of distributed object systems may be adapted for dynamically reconfigurable architectures. This approach answers many open questions concerning communication, interruption, and relocation of reconfigurable modules. It is explored by means of an extended Linux operating system in conjunction with a SystemC model of a dynamically reconfigurable FPGA

Energy and Coverage Aware Routing Algorithm in Self Organized Sensor Networks

This paper investigates the energy problem in sensor networks. After random deployment, nodes have to observe a region and transmit their sensor data to a central station. By checking redundancies in coverage and transmission with our XGAF algorithm presented here it is possible to shutdown the majority of nodes into sleep mode. Computation reduction in sleeping nodes and reduced communication results in increased network lifetime. This paper presents a novel routing algorithm which takes into account information concerning coverage and energy and using the advantages of scale free networks. Additionally, the algorithm allows nodes to work self organized. Thence, communication with the central station is reduced.

Design Flow on a Chip - An Evolvable HW/SW Platform

Partial dynamic reconfigurability of modern FPGAs holds the potential of realizing autonomous and highly flexible systems-on-chip (SoC). Current devices can be configured with several partial bitfiles and replace particular ones on demand. But these precompiled bitfiles seriously lack flexibility: they are hardly relocatable and not adjustable. In other words, they are tied to their original functional scope and location. This paper proposes an integration of the design flow onto the reconfigurable device itself to be capable of runtime reconfiguration and adaptation through modifications on the source code level. Thus, a network-on-chip (NoC) and a Linux operating system (OS) have been combined. The design flow is integrated into a feedback control system, which runs as an application under Linux. As a consequence, an evolvable platform emerges, which is capable of adapting autonomously to its dynamic environment and changing parameters

Trust-by-Wire in packet-switched networks: Calling line identification presentation for IP

During the last decades, the Internet has steadily developed into a mass medium with millions of users. On the one hand, newfangled services replace traditional ones. Naturally, these are thereby expected to offer at least the same features as their classical pendants, e.g., when VoIP replaces traditional fixed line telephone networks. On the other hand, the requirements on network infrastructures and services have changed. A reason for that is the lack of Trust-by-Wire in packet-switched IP networks. In traditional telephone networks, a phone number directly coheres with a physical line. This direct relationship is not given in modern packet-switched IP networks. An IP address does not identify a physical line! This paper presents a new mechanism, which guarantees Trust-by-Wire in packet- switched IP networks -called Internet Protocol-Calling Line Identification Presentation (IPclip). Unambiguous and trustworthy location information is added on the IP level. Firstly, IPclips general functionality is presented. Secondly, we discuss IPclip in the light of location-aware emergency calls in nomadic VoIP environments.

Countering phishing threats with trust-by-wire in packet-switched ip networks - a conceptual framework

During the last years, the Internet has grown into a mass-medium for communication and information exchange. Millions of people are using the Internet for business and in social life. Users can be reached easily and cost-effectively. Unfortunately the Internets open structure is the reason for its frequent misuse for illegal and criminal actions such as dissembling phishing attacks. Thus, anti-phishing techniques are needed to recognize potential phishing threats. But mostly these techniques are only of reactive nature, are soon circumvented by expert frauds, or are not efficient enough. This paper describes an anti-phishing framework. A concept for trust management and a mechanism called IPclip are presented. The main idea of IPclip is to guarantee trust-by-wire in packet-switched networks by providing trustworthy location information along with every IP packet. This information is used as supplementary and trustworthy trigger to identify potential phishing threats. Besides, the proposed framework allows for tracing the threats origin by using a set of location information.

Mapping a Pipelined Data Path onto a Network-on-Chip

During the last years, networks-on-chip (NoCs) have become a true alternative for the design of complex integrated systems-on-chip (SoC). Much effort has been spent for research on functionalities, mechanisms, and quality-of-service (QoS) features in NoCs. Hence, a broad and multi-faceted design space exists but leaves open, which mechanisms and design paradigms actually tip the scales for the chosen application domain. In this paper, we discuss the level of QoS needed in a specific NoC for a packet processing application. This is done in the light of preliminary investigations for the redesign of an existing packet processing system because that systems current architecture exhibits drawbacks regarding performance and further scalability. Therefore, we considered to take advantage of an NoC communication architecture. A simple NoC was developed, which knowingly omits sophisticated QoS mechanisms. Relying on the lessons, which have learned from the history and development of the Internet, we argue that a simple and plain NoC suffices for applications as the one discussed.

LoGen -- Generation and Simulation of Digital Logic on the Gate-Level via Internet

The Internet is omnipresent. Everyone uses the Internet for information retrieval and communication. It is part and parcel of everyday life and culture. This is also true for all levels of preschool and academic education as well as on-the-job training. Currently, providing learning objects on an electronic and personalized base is widely favored and - in the meantime-common practice. We present LoGen, a browser-based tool for the generation and simulation of digital, logic circuits on the gate-level via Internet. This tool is used as additional learning module for lectures and exercises at the Institute of Applied Microelectronics and Computer Engineering, University of Rostock. The feasibility of standard HTML for suchlike applications is pointed out. For the design of the tool, solely approved and well-established Internet-technologies have been used. It is especially feasible for so-called thin clients. It is shown that the Internet with its broad repertoire of basic functions and services is well suited for this kind of applications

IPclip: An architecture to restore Trust-by-Wire in packet-switched networks

During the last decades, the Internet has steadily developed into a mass medium. The target group radically changed compared to, e.g., the 90s. Because virtually everyone has access to the Internet, threats due to insecurity and anonymity reach critical levels and have to be tackled by both carriers and Internet Service Providers. Regaining trust-by-wire, comparable to classic fixed line telephones, could mitigate or even solve problems like Spam, Phishing, and the localization of VoIP emergency calls. This paper presents the hardware implementation of a new and highly flexible solution-Internet protocol-calling line identification presentation-which provides additional support for new services to restore peoplepsilas confidence into the Internet. Supported services are VoIP emergency calls, Spam detection and prevention, and phishing prevention. Already in the access network, the hardware adds unambiguous location information on the packetpsilas origin to IP packets. We document the hardware design of the solution. Furthermore, hardware consumption and performance of a prototype are presented.

A Structural Architecture for HW Packet Processing

In modern network applications and especially in Access Networks, the demands towards functionality and throughput are rising permanently. Furthermore, telecommunication carriers have different and changing requirements towards Access Network equipment. They are thus demanding a great deal of flexibility in IP-DSLAMS. To satisfy these various needs, highly flexible and particularly high performing packet processors are required. We propose an architecture for hardware modules, which joins the advantages of software and hardware solutions targeting packet processing. Our architecture provides a powerful and fast solution due to hardware implementation. Furthermore, it enables flexible and adaptive packet processors for different needs and configurations comparable to a software solution based on a network processor. This is accomplished without any overhead of unnecessary functionality and without the difficulties, which occur when it comes to adjusting pure ASIC packet processors to different tasks. Our architectural approach thus provides a good solution for packet processing.