Jochen Supper

Frequency dependencies of power noise

In this paper, frequency dependencies of delta-I noise caused by variations of the on-chip switching activity have been analyzed by simulations for a complex computer system board with multi-chip module, especially the impact of coincidences with resonances of the power distribution system. The switching frequency and the noise source waveform have been varied in case of a single delta-I step. For repeated delta-I steps the power noise dependencies on the repetition frequency, the duty cycle and the damping of the resonant loop have been analyzed. Simulations using switching current sources for on-chip switching have been confirmed by simulations with switching resistors plus de voltage source. Mid-frequency noise simulations using SPEED2000 and noise voltage measurements yield the same results within 6% for the first and second voltage droops and overshoots, if the real resistance of power/ground vias and module pins are included in the simulation.

Electronic packaging of the IBM System z196 enterprise-class server processor cage

In this paper, we describe the first- and second-level system packaging structure of the IBM zEnterprise® 196 (z196) enterprise-class server. The design point required a more than 50% overall increase in system performance (in millions of instructions per second) in comparison to its predecessor. This resulted in a new system design that includes, among other things, increased input/output bandwidth, more processors with higher frequencies, and increased current demand of more than 2,000 A for the six processor chips and two cache chips per multichip module. To achieve these targets, we implemented several new packaging technologies. The z196 enterprise-class server uses a new differential memory interface between the processor chips and custom-designed server memory modules. The electrical power delivery system design follows a substantially new approach using Vicor Factor Power® blocks, which results in higher packaging integration density and minimized package electrical losses. The power noise decoupling strategy was changed because of the availability of deep-trench technology on the new processor chip generation.

Simulations of frequency dependencies of delta-I noise

In this paper frequency dependencies of delta-I noise caused by variations in on-chip switching activity has been studied for a complex computer system board with multi-chip module, especially the impact of coincidences with resonances of the power distribution system. The switching cycle has been varied in case of a single delta-I step and the effect of repeated delta-I steps and variations of the delta-I repetition frequency and the duty factor have been analyzed.

Analysis and Mitigation of Parasitic Mode Conversion for Microstrip to Stripline Transitions

In this letter, the parasitic mode conversion that occurs at microstrip to stripline transitions is analyzed through electromagnetic simulations and an equivalent circuit including the parallel-plate impedance. It is shown that the excitation of plate modes can significantly impact transmission and crosstalk parameters, and that mitigation of mode conversion by the utilization of return vias is feasible.

Packaging design challenges of the IBM system z10 enterprise class server

This paper describes the system packaging and technologies of the IBM System z10™ high-end Enterprise Class server. This machine exceeds the multiprocessor performance of the previous system by 50%. A new generation of the IBM Elastic Interface was developed in order to maintain the increased interconnect signal speed of up to 2.93 Gb/s. Power control and power delivery to the multicore processors were a special challenge for the server packaging because of the high currents and the high number of voltage domains.

Thermal power plane enabling dual-side electrical interconnects for high-performance chip stacks: Concept

In this paper, a novel concept of dual-side electrical interconnects (EIC) to a chip stack is discussed. In this concept, a second laminate, called Thermal Power Plane (TPP), is attached through solder rails to the top chip of the stack. The TPP provides efficient heat removal and current feed in the out-of-plane and the in-plane direction, respectively. Accordingly, the number of electrical interconnects to the chip stack can be doubled, enabling higher off-stack communication. An interconnect count analysis was performed for a two-die stack with cores in the top and cache in the bottom chip. The power to the top and the bottom chip is provided from the TPP and the bottom laminate, respectively. In this case, all power through-silicon vias (TSVs) can be eliminated, which would otherwise cover 3.3% of the bottom chip area. In addition, the design of the TSVs can be optimized for signaling only. The use of two laminates also enables individual test & burn-in of the dies prior to stack formation, potentially improving the yield by joining only known good dies. The feasibility of the concept is supported by thermal and electrical finite-element analysis. An 8-layer coreless laminate with stacked build-up vias, extending between both sides of the substrate, was considered as implementation of the TPP. The thermal performance of the dual-side EIC topology outperforms that of the classical single-side EIC approach by 5 Kmm2/W, when considering bar-shaped copper planes in the TPP and elongated top interconnects, called rails. A voltage uniformity to the top chip of better than 2% of the supply voltage can be provided for all TPP designs.