Harry Barowski

Thermal power plane enabling dual-side electrical interconnects for high-performance chip stacks: Concept

In this paper, a novel concept of dual-side electrical interconnects (EIC) to a chip stack is discussed. In this concept, a second laminate, called Thermal Power Plane (TPP), is attached through solder rails to the top chip of the stack. The TPP provides efficient heat removal and current feed in the out-of-plane and the in-plane direction, respectively. Accordingly, the number of electrical interconnects to the chip stack can be doubled, enabling higher off-stack communication. An interconnect count analysis was performed for a two-die stack with cores in the top and cache in the bottom chip. The power to the top and the bottom chip is provided from the TPP and the bottom laminate, respectively. In this case, all power through-silicon vias (TSVs) can be eliminated, which would otherwise cover 3.3% of the bottom chip area. In addition, the design of the TSVs can be optimized for signaling only. The use of two laminates also enables individual test & burn-in of the dies prior to stack formation, potentially improving the yield by joining only known good dies. The feasibility of the concept is supported by thermal and electrical finite-element analysis. An 8-layer coreless laminate with stacked build-up vias, extending between both sides of the substrate, was considered as implementation of the TPP. The thermal performance of the dual-side EIC topology outperforms that of the classical single-side EIC approach by 5 Kmm2/W, when considering bar-shaped copper planes in the TPP and elongated top interconnects, called rails. A voltage uniformity to the top chip of better than 2% of the supply voltage can be provided for all TPP designs.