Stephen Gee

Effect of current crowding on void propagation at the interface between intermetallic compound and solder in flip chip solder joints

We propose a kinetic model to describe a pancake-type void propagation in flip chip solder joints due to current crowding in electromigration. The divergence of the vacancy fluxes at the interface between the solder and Cu6Sn5 leads to void formation and propagation along the interface between them. Based on the continuity condition, the void growth velocity is calculated. The theoretical calculations are in reasonable agreement with the experimental results.

Lead-Free and PbSn Bump Electromigration Testing

As the electronics industry continues to push for miniaturization, several reliability factors become vital issues. The demand for a high population of smaller and smaller solder bumps, while also increasing the current, have resulted in a significant increase in the current density. As outlined in the International Technology of Roadmap for Semiconductors (ITRS), this trend makes electromigration the limiting factor in high density packages. The heightened current density and correspondingly elevated operating temperatures are a critical issue in reliability since these factors facilitate the effects of electromigration. Therefore, as bump sizes continue to decrease, the study of electromigration reliability becomes crucial in order to understand and possibly prevent the causes of failure. A systematic study of electromigration in eutectic SnPb and Pb-free solder bumps was conducted in order to characterize the reliability of the Micro SMD package family. The testing includes both eutectic 63Sn-37Pb and 95.5Sn4.0Ag-0.5Cu solder bumps on an Al/Ni(V)/Cu under-bump-metallization. Mean-time-to-failure results are compared to Black’s Equation and cross-sections of the solder bumps are shown to analyze the mechanisms that led to failure.Copyright

A test chip design for detecting thin film cracking in integrated circuits

A reliability problem associated with integrated circuit assembly in molded plastic packages involves cracking in the deposited thin film layers on the top silicon surface. During thermal cycle testing, thermomechanical stresses resulting from differences in expansion coefficient can cause large relative displacements at the silicon/mold compound interface. The resulting die surface shear stresses are heavily concentrated at the corners and edges of the silicon die. These shear stresses can result in critical stress concentrations in the brittle passivation and interlayer dielectric films. This paper will report on a test chip design involving a matrix of crossing metal traces. This test chip has been designed to be sensitive to electrical leakage problems associated with thin film cracking. Two important quantities are measured. The first is electrical failure rate, which is determined as a function of metal width and proximity to the corners and edges of the die. The second is the extent over which cracking in the thin film layers progresses into the interior of the die. When overlaid on simple linear elastic finite elements models of stress, this locus of failure tends to follow lines of constant shear stress. This allows the assignment of a nominal stress value, critical in the collapse of microscopic thin film structures. >

Stress related offset voltage shift in a precision operational amplifier

In molded DIP packaging die attach stresses and stresses due to the contraction of the molding compound lead to a complex state of stress on the die surface where active device elements are located. This paper summarizes experimentation to reduce the effects of packaging stresses upon offset voltage shift in a precision operational amplifier. Variables examined include circuit location, low stress mold compounds, silicone gel coatings, side braze versus molded DIP assembly and post assembly trim.<<ETX>>