Stephen Keith Heinrich-Barna

FRAM sense amplifier with compensation for random and systematic offset

Sense Amplifiers have always been an integral part of an embedded memory design and operation. The decreasing process size, appetite for speed, low power, and smaller area all contribute to increased Sense Amplifier (SA) offset. In FRAM technologies, factors such as bitcell scaling, thermal depolarization [2], solder reflow processes [1], and state-dependent imprinting [2] all contribute to decreased signal margin available to the SA. Therefore, increase in SA offset coupled with decrease in signal margin translates into loss of yield and reliability. This paper introduces a modified SA circuit design that through introduction of localized and intentional asymmetrical capacitive loading, on state defining nodes, is shown to reduce the sample sigma and range of the SAs offset, improving the yield.

Low temperature endurance failures on flash memory

Write-erase cycling of flash memories has distinct failure signatures that have been thoroughly documented in the literature. A new mechanism has been uncovered when cycling at low temperatures. On the 65nm embedded flash technology, units exhibited a programming failure signature. However, further investigation verified that fail bits were fully programmed. Cause of failure was attributed to a non-classical hot carrier mechanism affecting an NMOS transistor in the sense circuitry. This was not expected as the Vds of the affected transistor was relatively low. TCAD simulations verified that the back bias on the transistor heated up electrons in the drain space charge region, generating secondary electrons from avalanche multiplication. The details of the failure mechanism, previously unpublished and unknown to current reliability tools, will be discussed and the corrective actions will be identified.

High resolution, self-compensated, sense amplifier for FRAM technology

Ferroelectric RAM (FRAM) is a non-volatile memory with fast, low power, high endurance, read and write operations. Hence, this technology remains an attractive choice for embedded system solutions. In this paper, we analyze Si data that initiated the effort to design a compensated Sense Amplifier (SA) with improved input offset-sigma. We evaluate the cost vs benefit tradeoffs associated with this metal-cap based approach to offset compensation. Lastly, we present design improvements, which will preserve the benefits of SA with compensation while reducing the cost. In this work we propose a self-compensated and high resolution SA, in 130nm FRAM technology, which will enable a more accurate and consistent delineation of smaller signal margins.

Analyzing single bit failure in SRAM with no visual defects

We present a simulation methodology to analyze single bit fails in SRAMs with no visual defect to account for the failure. Our approach generates the MOS IV curves for all six transistors of the failing bit cell and uses this data to simulate read, write and read-disturb failures. A good agreement with the tester data then establishes the basis for the failure even in the absence of any visual defect(s).