Stephen O'Kane

Design and implementation of a shared buffer architecture for a gigabit Ethernet packet switch

In this paper, the authors explored the design issues of shared buffer architecture capable of buffering fixed and variable sized packets for a 10G Ethernet switch. The design and implementation of a shared buffer circuit based on Xilinx Virtex 4 FPGA technology was presented. The proposed architecture is economic from the resource sharing point of view and is capable of supporting buffer bandwidths in excess of 31 Gbps using standard FPGA technology.

An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing

This paper presents the design and implementation of a fast shared packet buffer for throughput rates of at least 10 Gbps using RLDRAM II memory. A complex packet buffer controller is implemented on an Altera FPGA and interfaced to the memory. Four RLDRAM II devices are combined to store the packet data and one RLDRAM II device is used to store a linked-list of the packet memory addresses which is maintained by the packet buffer controller. The architecture is pipelined and optimised to combat the latencies involved with RLDRAM II technologies to enable a high performance low cost packet buffer implementation.

A Study of Shared Buffer Memory Segmentation for Packet Switched Networks

Classical shared buffer architectures are designed for variable sized packets and deploy memory segmentation for efficient resource management and to overcome memory fragmentation. There subsequently exists a tradeoff in selecting the most appropriate segment size due the variable sized nature of IP packets. In this paper, the segmentation tradeoffs for packet switched networks are investigated and recommendations for appropriate segment sizes are given.

An investigation into the design of high-performance shared buffer architectures based on FPGA technology with embedded memory

The asynchronous nature of packet based communication demands efficient management of buffer resources at network nodes. Shared buffer architectures consequently become one of the dominating constructs of modern routers and switches. This work investigates new and existing shared buffer architectures that are ideal for emerging FPGA technologies with embedded memory.

Implementing high speed IP address lookups in hardware

The issue of accelerating IP address lookup is critical for the next generation of Internet routers. This paper discusses the benefits that a hardware targeted solution has over more traditional solutions. An investigation is made into two proposed architectures using different approaches, namely a search trie and a hash based architecture. The advantages of each approach and how they utilize the unique advantages hardware based solutions can offer are investigated.

The design and implementation of a shared packet buffer architecture for fixed and variable sized packets

In this paper, we explore the issues of designing a shared buffer architecture for buffering fixed and variable sized packets. The design and implementation of a shared buffer circuit based on Altera Stratix 2 FPGA technology is presented. The proposed architecture is economic from the resource sharing point of view and is capable supporting buffer bandwidths in excess of 6 Gbit/s using standard FPGA technology.