Steve Curtis

A sub 2W low power IA Processor for Mobile Internet Devices in 45nm Hi-K metal gate CMOS

This paper describes a low power Intelreg Architecture (IA) processor specifically designed for mobile internet devices (MID). The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32 KB instruction and 24 KB data L1 caches, independent integer and floating point execution units, a 512 KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) front-side-bus (FSB). The design contains 47 million transistors in a die size under 25 mm2 manufactured in a 9-metal 45 nm CMOS process. Thermal design power (TDP) consumption is measured at 2 W, 1.0 V, 90degC using a synthetic power-virus test at a frequency of 1.86 GHz.

Early Power-Aware Design & Validation: Myth or Reality?

Design for low power is crucial for developing and optimizing complex SoCs. Typically, power issues are tackled at the gate-level and backend stages, disconnected from micro-architectural power features or RTL. However, there is growing debate about which stage of the design process is best for dealing with power issues. Leaders associated with the EDA industry and R&D realm will debate whether early power-aware design and validation is viable, and will hold a spirited discussion to determine at which stage of the design process power issues should be tackled: gate level and below, or system level. They will cover various issues involved in automating or establishing a well understood flow/process that delivers quality results, and also will consider organizational hurdles. Attendees will leave this session armed with key questions and valuable insights, and will be challenged to consider if they should change their approach to low-power design.