Binta M. Patel

A sub 2W low power IA Processor for Mobile Internet Devices in 45nm Hi-K metal gate CMOS

This paper describes a low power Intelreg Architecture (IA) processor specifically designed for mobile internet devices (MID). The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32 KB instruction and 24 KB data L1 caches, independent integer and floating point execution units, a 512 KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) front-side-bus (FSB). The design contains 47 million transistors in a die size under 25 mm2 manufactured in a 9-metal 45 nm CMOS process. Thermal design power (TDP) consumption is measured at 2 W, 1.0 V, 90degC using a synthetic power-virus test at a frequency of 1.86 GHz.

Next generation Intel® ATOM™ processor based ultra low power SoC for handheld applications

Lincroft, the next generation Intel® ATOM™ processor based SoC specifically designed for smartphones, is fabricated in 45nm Hi-K metal gate CMOS. The design contains 140 million transistors in a die size of 65 mm2. Thermal design power (TDP) consumption is measured at 1.25W at 90°C at a frequency of 1.20GHz. Low power IO interfaces such as LPDDR1/DDR2, cDMI to IOH and cDVO for display are deployed to meet unique handheld SoC needs while consuming ultra low power. Clock architecture and clock distribution is configured with special power reduction features. As part of the extensive low power methodology, the chip is divided into numerous power domains with on die distributed powergates to reduce both active and standby power. Measured data shows up to 50X reduction in standby power. Silicon data shows dramatically low power in sleep and deeper sleep standby power states.