Steven Decker

A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC

A 16-bit 125 MS/s pipeline analog-to-digital converter (ADC) implemented in a 0.18 ¿m CMOS process is presented in this paper. A SHA-less 4-bit front-end is used to achieve low power and minimize the size of the input sampling capacitance in order to ease drivability. The ADC includes foreground factory digital calibration to correct for capacitor mismatches and dithering that can be optionally enabled to improve small-signal linearity. This ADC achieves an SNR of 78.7 dB, an SNDR of 78.6 dB and an SFDR of 96 dB with a 30 MHz input signal, while maintaining an SNR > 76 dB and an SFDR > 85 dB up to 150 MHz input signals. Further, with dithering enabled the worst spur is <-98 dB for inputs below -4 dBFS at 100 MHz IF. The ADC consumes 385 mW from a 1.8 V supply.

A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS

Successive-approximation ADCs (SARs) have excelled in two spaces: in very-high-SNR applications where the precision and stability of capacitors are leveraged along with the use of large signal swings and in high-speed, low-resolution applications in which the SARs low power and simplicity has enabled high levels of time-interleaving. In between, ADCs with greater than 10 effective bits and sample rates above 20MS/s are typically not based on the SAR architecture. The sequential nature of the SAR algorithm makes it difficult to achieve both high speed and high accuracy, as increasing the resolution requires each bit decision to be both faster and lower noise. This paper presents a SAR that overcomes some of the conventional speed limitations; it uses a 1.2V-only supply and achieves >70dB SNDR at 80MS/s, which extends the state of the art while maintaining comparable FoM.

A 16b 125MS/s 385mW 78.7dB SNR CMOS pipeline ADC

Todays communication systems require high-performance low-cost ADCs with emphasis on low power, and the ability to IF-sample to reduce receiver complexity. Further, the often-overlooked metric of small-signal linearity, quantified by SFDR for less-than-full-scale inputs is important, especially in the presence of large interferers. This 16b pipeline ADC achieves 78.7dB SNR, 78.6dB SNDR and 96dB SFDR at 125MS/s with a 30MHz input, while dissipating 385mW from a 1.8V supply. The ADC quantizes inputs up to 150MHz with an SNR ≫76dB and an SFDR ≫85dB, has a jitter of 65fs and accepts 2Vpp-diff inputs. Further, with dithering enabled the worst spur is ≪−98dB for inputs below −4dBFS at 100MHz IF. The ADC is fabricated in a 1P5M 0.18µm CMOS process.

A CMOS analog front-end chip-set for mega pixel camcorders

In modern CCD video camera systems, packaging and optical requirements constrain the CCD to be mounted close to the camera lens, often on a board separate from the main signal processing. In this configuration, the analog signal from the CCD must be driven across a flexible cable to the main board, where analog pre-processing is performed. In previous camera generations, the challenge was simply to integrate all of the analog functions onto a single CMOS chip compatible with low voltage supplies. This results in low-cost low-power system partitioning now widely used for consumer CCD camera systems. As consumer CCD sensors move toward higher resolution, however, this conventional integration has weaknesses. This paper shows a modified analog front-end integration for high-speed CCD interface to overcome the problems of conventional partitioning.

A 14b 74MS/s CMOS AFE for True High-Definition Camcorders

A 14b 74MS/s CMOS AFE is designed for true high-definition camcorder applications. This is the first published AFE capable of high-definition sample rates. The AFE operates from a 1.8V supply, achieves 78dB peak SNR, 1.4V input range, and dissipates 70mW