Steven K. Groothuis

Packaging effects on reliability of Cu/low-k interconnects

Chip-packaging interaction is becoming a critical reliability issue for Cu/low-k chips during assembly into a plastic flip-chip package. With the traditional TEOS interlevel dielectric being replaced by much weaker low-k dielectrics, packaging induced interfacial delamination in low-k interconnects has been widely observed, raising serious reliability concerns for Cu/low-k chips. In a flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/low-k interconnect structure inducing large local deformation to drive interfacial crack formation. In this paper, we summarize experimental and modeling results from studies performed in our laboratory to investigate the chip-package interaction and its impact on low-k interconnect reliability. We first review the experimental techniques for measuring thermal deformation in a flip-chip package and interfacial fracture energy for low-k interfaces. Then results from three-dimensional finite element analysis (FEA) based on a multilevel submodeling approach in combination with high-resolution moire/spl acute/ interferometry to investigate the chip-package interaction for low-k interconnects are discussed. Packaging induced crack driving forces for relevant interfaces in Cu/low-k structures are deduced and compared with corresponding interfaces in Cu/TEOS and Al/TEOS structures to assess the effect of ILD on packaging reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low-k structures.

Chip-packaging interaction: a critical concern for Cu/low k packaging

Chip-packaging interaction is becoming a critical reliability issue for Cu/low k chips during package assembly. With the traditional TEOS interlevel dielectric being replaced by much weaker low k dielectrics, packaging induced interfacial delamination in low k interconnects has been widely observed, raising serious reliability concerns for Cu/low k chips. In a flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/low k interconnect structure inducing large local deformation to drive interfacial crack formation. In this paper, we will first review the experimental techniques for package thermal deformation measurement and interfacial fracture energy measurement for low k interfaces. Then 3D finite element analysis (FEA) based on a multilevel sub-modeling approach in combination with high-resolution Moire interferometry is employed to examine the packaging effect on low k interconnect reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low k structures. Possible solutions and future study are discussed.

Packaging effect on reliability for Cu/low k structures

The packaging process can significantly increase the driving force for interfacial delamination and seriously impact the reliability of the low k chip. In this study we investigated the packaging effect due to die attach process where a high thermal load occurs during solder reflow before underfilling. With the high thermal load and without the underfill, the chip-package interaction is maximized and can be most detrimental to low k chip reliability. SiLK and MSQ are two low k dielectrics investigated in this paper to find the influence of low k properties on packaging reliability. In addition to different low k dielectrics, we investigated the effects due to the substrate material, die size and solder materials, including lead-free solder. The packaging effect was found to be more significant for flip-chip packages with lead-free solder than eutectic solder and high lead solder. Flip-chip packages with a ceramic substrate were found to have a smaller packaging effect than that with an organic substrate. Increasing the die size in a package increases the crack driving force for low k interfacial delamination, as expected. Packaging effect was smaller for the Cu/MSQ structure than the Cu/SiLK structure and the difference can be attributed to the higher Youngs modulus of the MSQ material.

Numerical simulation of silicon wafer warpage due to thin film residual stresses

Wafer warpage is one of the most important challenges in the fabrication of modern electronic devices. Other challenges include handling, tool faults, and misalignments and even wafer breakage. The wafer warpage translates into die warpage that has a remarkable impact on die pick, stack and attach. This paper describes the work performed to simulate the silicon wafer warpage as a function of the wafer thickness and the film stresses using the commercial finite element code ABAQUS. The model accounts for the silicon anisotropy to better simulate the deformation. The computed values of the warpage were compared with experimental data and showed good correlation. The numerical model developed can be used to better understand the relation between the film stress and the wafer warpage. Furthermore it can be used to predict the warpage based on the wafer thickness and the film stress, which can help mitigate the warpage by depositing films to reduce the overall wafer warpage.

Numerical simulation of heat generation during the back grinding process of silicon wafers

The optimization of grinding parameters for silicon wafers is necessary in order to increase the reliability of electronic packages. Grinding is a mechanical process performed on silicon wafers during which heat is generated. The amount of heat generated affects the reliability of the wafer, and implicitly that of the final product. This paper describes the work performed to simulate the heat generated during a back grinding process for silicon wafers using the commercial finite element code ABAQUS. The grinding of a silicon wafer with a thickness of 60 μm mounted on a carrier wafer using bond adhesive material was simulated. The heat generated is caused by the friction between the grinding wheel and the backside of the silicon wafer. The computed temperature change due to friction in the wafer was compared with experimental and numerical values, and showed a good correlation. The numerical model developed can be used to better understand the local grinding temperature in the wafers and to estimate the effect of the grinding parameters on the temperature rise.

Computer-aided engineering (CAE) applications in semiconductor device manufacturing and reliability

With the ever increasing complexity of semiconductor device designs, the need for designed-in manufacturability and reliability continues to present a challenge for successful semiconductor product introduction. Technology computer-aided design (TCAD) software tools provide the needed device physics simulations for both functional and performance requirements. However, an innovative approach of using both TCAD tools and computer-aided engineering (CAE) simulation tools (e.g., used in other areas of physics and mechanical engineering) can provide a comprehensive solution to wafer fabrication and device reliability efforts

Package and board level study for a thin small outline package (TSOP) using compact components

A detail model of 54 lead Thin Small Outline Package (TSOP) was created in Flotherm and validated against experimental data for natural convection and forced convection environments. Next, a compact two-resistor (2R) model was created in Flotherm using compact smart parts. Values of junction-to-case and junction-to-board resistances were taken from experiments. Both the detailed model and the compact model were mounted on a 4-layered standard JEDEC board for natural convection in a standard JEDEC enclosure. With a nominal power of 0.75W applied at the junction, the detailed model and the 2R compact model showed a very good agreement. The results also compared well with experimental data. Next, two models were developed; a detailed model and a corresponding equivalent 2R compact model were mounted on a 4-layered standard JEDEC board and simulated for forced convection with an air velocity of 1 m/s. With a nominal power of 0.75 W applied at the junction, maximum junction temperatures were computed and once again showed very good agreement. Experimental data for forced convection indicated that the maximum junction temperature was in good agreement to the compact model. The study was further extended to do a board level analysis where the detailed TSOP models were mounted on a 6-layered standard DIMM board. In the single sided board arrangement nine such compact models were mounted on one side of the board and maximum junction temperature was noted. Then, the detailed models were replaced by compact models and simulated for forced convection with an air velocity of 1 m/s. Good agreement between detailed model and compact model was seen for the board level analysis. Further the compact models were simulated for a double-sided arrangement in which eighteen such compact models were mounted nine on each sided of the board. The assembly was simulated for forced convection with an air velocity of 1 m/s. Nominal power applied at junction for each of the eighteen modules was 0.3 W. Maximum temperature for the double sided arrangement of DIMM board was thus computed.Copyright