Steven Novak

Transparent indium gallium zinc oxide transistor based floating gate memory with platinum nanoparticles in the gate dielectric

A transparent memory device has been developed based on an indium gallium zinc oxide thin film transistor by incorporating platinum nanoparticles in the gate dielectric stack as the charge storage medium. The transfer characteristics of the device show a large clockwise hysteresis due to electron trapping and are attributed to the platinum nanoparticles. Effect of the gate bias stress (program voltage) magnitude, duration, and polarity on the memory window characteristics has been studied. Charge retention measurements were carried out and a loss of less than 25% of the trapped elec-trons was observed over 104 s indicating promising application as nonvolatile memory.

Platinum Nanoparticles Grown by Atomic Layer Deposition for Charge Storage Memory Applications

This paper explores platinum nanoparticle formation during the early stages of growth by atomic layer deposition. Particle size and distribution can be controlled by altering growth parameters. The particles show excellent temperature stability up to 900°C as examined by transmission electron microscopy and in situ heating. Capacitance-voltage and charge retention measurements demonstrate the memory effect in metal-oxide-semiconductor capacitors with embedded nanoparticles. The size, density, charge storage, and temperature stability of the platinum nanoparticles make them attractive for use as charge storage layers for nonvolatile memory devices.

Investigation of the Origin of

The role of La₂O₃ capping in the <i>VT</i>/<i>V</i>_FB shift with various high- <i>k</i> and metal gate electrodes was systematically investigated. It was found that the La concentration at the high-<i>k</i>/SiO₂ interface is mainly responsible for the <i>VT</i>/<i>V</i>_FB modulation in NMOS devices, whereas the effect of the host high-<i>k</i> and gate electrodes on <i>VT</i>/<i>V</i>_FB is minimal. A 400-mV shift in <i>VT</i> from the control HfO₂ device with minimal degradation in mobility was obtained when a La₂O₃ layer was inserted between the high-<i>k</i> and SiO₂ layers. It was also found that the incorporation of La₂O₃ in the dielectric stack improves device reliability in terms of breakdown and positive-bias temperature instability characteristics. The main key for the <i>V</i>_FB shift is the ability of La diffusion through the host high-<i>k</i> material.

V_{T}/V_{\rm FB}

The effective work function of PMOS metal gate electrode as a function of intentionally altered HfO2 surfaces was investigated. The impact of capping layers, diffusion barriers and interfacial layers on the final work function was also examined. The factors responsible for the change in the effective work function after subsequent thermal treatments were identified and routes to maintain the high effective work function have been demonstrated

Modulation by

This letter investigates the work function tuning of nickel/gadolinium (Ni/Gd) fully silicided (FUSI) gate electrodes on HfSiOx dielectrics. It was found that as the percentage of Gd in the Ni/Gd increased from 10% to 30%, the effective work function value after a one-step 450-degC FUSI anneal decreased from 4.75 to 4.35 eV. In addition, the presence of Gd also resulted in lowering of equivalent oxide thickness (EOT) values. The mechanism for a decreased EOT is attributed to the reduction of low-kappa interfacial layers by the presence of Gd in the gate stack. The decrease in work function is attributed to the creation of oxygen vacancies within the high-kappa layer created by the presence of Gd layer.

\hbox{La}_{2}\hbox{O}_{3}

Lanthanum silicate has many properties making it promising as a high-k gate dielectric for CMOS or advanced capacitor applications. For example, the amorphous phase has good high temperature stability, and the reaction of La2O3 with SiO2 has proven a means of eliminating interface SiO2 after low temperature processing; resulting in MIS devices with a combination of low EOT values (~0.63 nm) and low leakage at Vfb+1 (~0.1 A/cm). However, reliability and lifetime characteristics of lanthanum silicate have been largely unstudied. These are important specifically for lanthanum silicate due to the propensity of La to form hydroxides and carbonates.

Capping Layer Approaches for NMOS Application: Role of La Diffusion, Effect of Host High-

We present two new ternary alloy silicides with tunable work function ranging between 4.27eV to 4.7eV and 4.8eV to 5.0eV respectively for dual metal gate CMOS applications. NixTa1-xSi gates were investigated for NMOS and NixPt1-xSi gates were investigated for PMOS applications on SiO2, HfO 2 and HfSiOx dielectrics. A large degree of tuning was observed on SiO2 however the tuning range decreased as Hf content of the dielectric increased. It was also found that the thermal stability of nickel silicide was enhanced due to the incorporation of tantalum. Device results demonstrate thermally stable characteristics at 900degC, making them eligible candidate for gate first application. X-ray diffraction (XRD) confirmed presence of alloy silicide phases that were responsible for the work function tuning

k

It was found that the structural properties with gadolinium (Gd) and europium (Eu) incorporation into nickel (Ni) fully silicided (FUSI) gate electrodes are markedly different and resulted in different degrees of effective work function modulation. It was found that Ni–Gd alloys tend to form stable compounds during silicidation and produced a Si-rich layer with amorphous/nanocystalline structure near the FUSI gate electrode/high-k dielectric interface. This compositional and structural change is the main mechanism responsible for effective work function modulation with Gd incorporation. However, in the case of Europium, Eu atoms tend to segregate outside the Ni-FUSI layer during silicidation and resulted in a uniform NixSiy layer with Eu pile-up layer at the FUSI gate electrode/high-k dielectric interface. This pile-up is believed to be the main cause of effective work function modulation with Eu incorporation. It was also found that the incorporation of Gd and Eu metals into Ni-FUSI gate can remotely scavenge the interfacial oxide layer resulting in lower equivalent oxide thickness (EOT) of the device.

Layer, and Interface Properties

We have investigated the effect of ultrathin Al-Ta-based capping layers on HfO2 and experimentally demonstrated that, with proper Al and Ta composition, an AlTaO capping layer is a good candidate dielectric for PMOSFET devices. Lower threshold voltage and significantly improved mobility were observed with AlTaO capping without degrading the dielectric properties. The addition of Ta in an AlTaO structure produces d-states in the Al2O3 matrix, resulting in an additional VT shift toward the PMOS band edge. This AlTaO capping layer not only modulates the device VT suitably for PMOS applications but also retards Al diffusion through the HfO2 layer, preventing Al-caused mobility degradation. Furthermore, the incorporation of a capping layer can improve reliability characteristics during the negative bias stress.