Subhashis Majumder

Path delay testing: variable-clock versus rated-clock

There are two methods for applying path delay tests to a sequential circuit. We show that all path delay faults that can affect the rated-clock operation of the circuit are testable by the variable-clock method. Also, all path delay faults that are untestable by the variable-clock method are, in fact, untestable by the rated-clock method. However, some faults tested by the variable-clock method may be incapable of affecting the rated-clock operation. Our study is based on a finite-state machine model in which fault-free transitions are shown by green arcs. Faulty transitions are shown by red arcs. A test traverses successive arcs until a faulty output occurs. A variable-clock test can exercise more flexibility in selecting from green and red arcs. It can cover all functional paths, but may find only a proper subset of untestable paths. Our analysis assumes a delay fault, consisting of either a singly-testable path or multiply-testable paths, and hence corresponds to non-robust detection.

Hot spots and zones in a chip: a geometrician's view

In this paper we have proposed geometric models that are employed to devise a scheme for identifying the hot spots and zones in a chip. These spots or zones need to be guarded thermally to ensure performance and reliability of the chip. Two different models, namely continuous and discrete, are presented to take into account whether the 2D plane of the chip floor is gridless or a uniform grid, thereby reflecting on the possible locations of heat sources and the target observation points. The experimental results for both the domains - continuous and discrete, establish that a region, which does not contain any heat source, may become hotter than other regions containing thermal sources. Thus a hot zone may appear away from the hot spots, and placing heat sinks on the active thermal sources alone may not suffice to tackle thermal imbalance.

Voronoi based location aware collaborative filtering

Recommender systems help users in making decisions by recommending items of interest like movies, music, books, news, images, web pages, etc. to them. Collaborative filtering is one of the most widely studied and widely used techniques behind recommendation algorithms. It tries to recommend items to users based on user-user or item-item similarities computed from existing data. In this work, we propose a recommendation algorithm that takes the users location into account. The algorithm uses Voronoi Diagrams which are widely used in Computational Geometry to decompose a metric space into regions based on distances from a specified finite set of points. We have tested the algorithm on the MovieLens dataset.

Hierarchical partitioning of VLSI floorplans by staircases

This article addresses the problem of recursively bipartitioning a given floorplan F using monotone staircases. At each level of the hierarchy, a monotone staircase from one corner of F to its opposite corner is identified, such that (i) the two parts of the bipartition are nearly equal in area (or in the number of blocks), and (ii) the number of nets crossing the staircase is minimal. The problem of area-balanced bipartitioning is shown to be NP-hard, and a maxflow-based heuristic is proposed. Such a hierarchy may be useful to repeater placement in deep-submicron physical design, and also to global routing.

Partitioning VLSI floorplans by staircase channels for global routing

This paper identifies a new problem of geometric partitioning of VLSI floorplans, called mincost staircase partitioning. We propose a framework for channel definition in global routing. In a VLSI floorplan, the isothetic rectangular circuit modules are placed on a 2-D floor with nets attached to each block. The objective of global routing is to determine the channels through which the terminals attached to different modules belonging to the same net are connected. Here we have mapped the global routing problem into a series of hierarchical staircase channel routing. To minimize the routing congestion, in each level of hierarchy we find a monotone staircase channel minimizing the number of distinct nets, having terminals on both sides of the channel. We give an O(n/spl times/k) time algorithm for the two-terminal net problem, where n and k are the number of blocks and distinct nets respectively. For multi-terminal nets the time complexity is O((n+k)/spl times/T), T being the total number of terminals on the floor.

Finding Influential Nodes in Social Networks Using Minimum k-Hop Dominating Set

Challenges in social interaction networks are often modelled as graph theoretic problems. One such problem is to find a group of influential individuals of minimum size or the initial seed set in a social network, so that all the nodes in the network can be reached with only one hop from the seeds. This problem is equivalent to finding a minimum dominating set for the network. In this paper, we address a problem which is similar to finding minimum dominating set but differs in terms of number of hops needed to reach all the nodes. We have generalized the problem as k-hop dominating set problem, where a maximum of k hops will be allowed to spread the information among all the nodes of the graph. We show that the decision version of the k-hop dominating set problem is NP-complete. Results show that, in order to reach the same percentage of nodes in the network, if one extra hop is allowed then the cardinality of the seed set i.e. the number of influential nodes needed, is considerably reduced. Also, the experimental results show that the influential nodes can be characterized by their high betweenness values.

Spread of information in a social network using influential nodes

Viral marketing works with a social network as its backbone, where social interactions help spreading a message from one person to another. In social networks, a node with a higher degree can reach larger number of nodes in a single hop, and hence can be considered to be more influential than a node with lesser degree. For viral marketing with limited resources, initially the seller can focus on marketing the product to a certain influential group of individuals, here mentioned as core . If k persons are targeted for initial marketing, then the objective is to find the initial set of k active nodes, which will facilitate the spread most efficiently. We did a degree based scaling in graphs for making the edge weights suitable for degree based spreading. Then we detect the core from the maximum spanning tree (MST) of the graph by finding the top k influential nodes and the paths in MST that joins them. The paths within the core depict the key interaction sequences that will trigger the spread within the network. Experimental results show that the set of k influential nodes found by our core finding method spreads information faster than the greedy k -center method for the same k value.

ON FINDING A STAIRCASE CHANNEL WITH MINIMUM CROSSING NETS IN A VLSI FLOORPLAN

A VLSI chip is fabricated by integrating several rectangular circuit blocks on a 2D silicon floor. The circuit blocks are assumed to be placed isothetically and the netlist attached to each block i...

On delay-untestable paths and stuck-fault redundancy

We explore non-robust untestability of paths based on redundant stuck-at faults. Such untestability classification is necessary for a path to be ignored in timing verification and delay testing. A recent result states that redundant stuck-at-0 (s-a-0) and stuck-at-1 (s-a-1) faults of a line imply untestability of rising and falling delay faults, respectively, for all paths through that line. We find that this result only establishes robust untestability of paths. Starting with known examples, where a non-robust test can exist for some paths that pass through the site of a redundant stuck-at fault, we examine various classes of stuck-at fault redundancies. We prove that: (1) an unexcitable or undrivable redundant s-a-0 (s-a-1) fault will make all paths through the fault site non-robustly delay-untestable for rising (falling) transition, and (2) an unobservable fault site (causing both s-a-0 and s-a-1 faults to be redundant) can only classify the passing paths as robustly delay-untestable, Finally, we show that two singly-untestable paths, passing through the sites of separate redundant single stuck-at faults, may form a multiply-testable pair of paths provided the two redundant single stuck-at faults have a multi-fault test.

Simulation-based method for optimum microfluidic sample dilution using weighted mix-split of droplets

Digital microfluidics has recently emerged as an effective technology in providing inexpensive but reliable solutions to various biomedical and healthcare applications. On-chip dilution of a fluid sample to achieve a desired concentration is an important problem in the context of droplet-based microfluidic systems. Existing dilution algorithms deploy a sequence of balanced mix-split steps, where two unit-volume droplets of different concentrations are mixed, followed by a balanced-split operation to obtain two equal-sized droplets. In this study, the authors study the problem of generating dilutions using a combination of (1 : 1) and (1:2) mix/split operations, called weighted dilution (WD), and present a layout architecture to implement such WD-steps. The authors also describe a simulation based method to find the optimal mix-split steps for generating a dilution under various criteria such as minimisation of waste, sample, or buffer droplets. The sequences can be stored in a look-up table a priori, and used later in real time for fast generation of actuation sequences. Compared with the balanced (1:1) model, the proposed WD scheme reduces the number of mix-split steps by around 22%, and the number of waste droplets, by 18%.