Sabyasachee Banerjee

Image steganography by closest pixel-pair mapping

Steganography is one of the important and elegant tools used to securely transfer secret message in an imperceptible manner. Visual Steganography is another added feature of it. It is the steganographic method involving multimedia files like image, video etc. to hide a secret message. However this method may result in the distortion of the colour frequencies of the cover image which is predictable by some analysis. Here in this paper we have proposed a method for steganography which results in absolutely no distortion of the cover image. The proposed image is independent of the size of the cover image and the secret image i.e. a larger image can be hidden in a smaller image. The proposed method also uses AES Encryption for secure transfer of the stego-key. The nexus of this cover image and the encrypted data serves the purpose of secure transfer of secret data.

A Graph-Based 3D IC Partitioning Technique

Netlist partitioning is an important part of the physical design of 3D IC chips. Each subcircuit corresponding to a partition is subsequently assigned to a suitable device layer in the design phase. This paper proposes a netlist partitioning technique that intends to minimize the number of inter-layer interconnections while maintaining the area constraints. This, in turn, will minimize the area and cost associated with the Through-Silicon Vias (TSVs) needed in the design. The proposed method starts with an BFS-based initial solution and then improves iteratively using a heuristic. Experimental results demonstrate that by reassigning some modules to other layers, our algorithm could achieve up to 45% reduction in the number of TSVs on several benchmark circuits compared to earlier approaches. The resulting increase in floor area due to movement of modules a cross layers, is almost compensated by the decrease in TSV-area. Thus while satisfying the area-constraints, it allows us to reduce the number of TSVs as well as the IR-drop and delay associated with the vias.

Partitioning-based test time reduction for core-based 3DICs

To maintain the ever increasing demand for compaction as well as performance, 3D ICs were introduced. They have some additional advantages over their 2D counterparts in various aspects like heterogeneous integration, higher frequency, lesser interconnect length and increased bandwidth. Testing of core-based dies in 3D-SOCs poses many new challenges. This paper describes an automated post-bond core-based 3D SOC testing technique, under constraints on TAM width and number of available TSVs. We have conducted the experiments on the ITC 02 SOC test benchmarks and have compared the test times with that of earlier works to show the efficacy of our algorithm. Our partitioning-based algorithm exhibits much better performance compared to its earlier counterparts.

Honey Bee Based Vehicular Traffic Optimization and Management

Traffic densities in highly populated areas are more prone to various types of congestion problems. Due to the highly dynamic and random character of congestion forming and dissolving, no static and pre deterministic approaches like shortest path first (SPF) etc., can be applied to car navigators. Sensors are adequate here. Keeping view in all the above mentioned factors, our contributions in this paper include the development of a novel Bio Inspired algorithm on multiple layers to solve this optimization problem, where, car routing is handled through algorithms inspired by nature [Honeybee behavior]. The experimental results obtained from the implementation of the proposed algorithm are quite encouraging.

Speed Optimization in Unplanned Traffic Using Bio-Inspired Computing and Population Knowledge Base

Bio-Inspired Algorithms on Road Traffic Congestion and safety is a very promising research problem. Searching for an efficient optimization method to increase the degree of speed optimization and th increasing the traffic Flow in an unplanned zone is a widely concerning issue. However, there has been a limited research effort on the optimization of the lane usage with speed optimization. The main objective of this article is to find avenues or t echniques in a novel way to solve the problem optimally using the knowledge from analysis of speeds of vehicles, which, in turn will act as a guide for design of lanes optimally to provide better optimized traffic. The accident factors adjust the base mode l estimates for individual geometric design element dimensions and for traffic control features. The application of these algorithms in partially modified form in accordance of this novel Speed Optimization Technique in an Unplanned Traffic analysis techni que is applied to the proposed design and speed optimization plan. The experimental results based on real life data are quite encouraging.

Retracted: Speed Optimization in an Unplanned Lane Traffic Using Swarm Intelligence and Population Knowledge Base Oriented Performance Analysis

Comparative Analysis of Speed Optimization Technique in Unplanned Traffic is a very promising research problem. Searching for an efficient optimization method to increase the degree of speed optimization and thereby increasing the traffic flow in an unplanned zone is a widely concerning issue. However, there has been a limited research effort on the optimization of the lane usage with speed optimization. This paper presents a novel technique to solve the problem optimally using the knowledge base analysis of speeds of vehicles, using partial modification of Swarm Intelligence which, in turn will act as a guide for design of lanes optimally to provide better optimized traffic with less number of transitions between lanes.

Bio-inspired Computational Optimization of Speed in an Unplanned Traffic and Comparative Analysis Using Population Knowledge Base Factor

Bio- inspired Computational Optimization of Speed in Unplanned Traffic and the comparative analysis is a very promising research problem. Searching for an efficient optimization method or technique to formulate optimal solution of a given problem in hand is very challenging and thereby to increase the traffic flow in an unplanned zone is a widely concerning issue. However, there has been a limited research effort on the optimization of the lane usage with speed optimization. This paper presents a novel technique to solve the problem optimally using the knowledge base analysis of speeds of vehicles, using partial modification of Bio Inspired Algorithm (Ant Colony Optimization) which, in turn will act as a guide and baseline for designing lanes optimally to provide better optimized traffic with less number of transitions between lanes.

Power-aware test optimization for core-based 3D-SOCs under TSV-constraints

While 3D chips open up versatile potentialities in compact system design, they pose the challenge of testing the composite system, which consists of multiple cores, logic, and memory, interconnected across different layers of the chip. The test strategy for such chips must also take into account the issues of inherent power and thermal constraints, design of test-access mechanism (TAM), and the decision concerning pre-bond and post-bond test choices. Additionally, for post-bond testing, the constraints imposed by the limited use of TSVs, worsen the controllability and observability of the cores that are accessed through the inter-layer scan-paths. Thus, while designing the TAM architecture, the optimization of overall test time under the constraints of power and TSV-count, is needed. This paper presents a new technique for test-time reduction in post-bond core-based 3D-SOCs, considering certain constraints on test power and TAM width (i.e., bounds on TSVs). The proposed algorithm runs much faster compared to prior art, and our results on several ITC02 benchmarks reveal significant reduction in test-time for most of the cases.

A thermal aware 3D IC partitioning technique

On-chip power density plays a major role in case of Highperformance VLSI circuits. 3D chips have significantly larger power densities compared to their 2D counterparts due to increased scaling of technology and also increased number of components with higher frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. Thermal problems and limitations on inter-layer via (TSV) densities are important design constraints on three-dimensional integrated circuits (3D ICs). In this paper we introduce an algorithm where the modules with relatively high power densities are placed at the bottom layer and subsequently modules with relatively less power densities are placed on more higher layers. The temperatures of the layers vary in a non-increasing manner from the bottommost layer to the topmost layer to ensure efficient heat dissipation of the whole chip, which means we may require lesser number of heat TSVs to dissipate heat. Along with this thermal aware partitioning technique, we also tried to minimize the number of inter-layer vias (Signal TSVs) by swapping some modules across layers, in exchange of little increment in the area of the layer that has the maximum area in the circuitry. The experimental results we got are quite encouraging.