Subramanian Ramesh

The design, analysis, and development of highly manufacturable 6-T SRAM bitcells for SoC applications

We present here an extensive static random access memory (SRAM) bitcell development methodology that has led to the qualification and production of the smallest 6-T SRAM bitcell reported in 0.13-/spl mu/m CMOS technology. No additional processing steps were employed in accomplishing this result. Such a methodology is being extended also to subsequent technology generations. The development efforts included the electrical evaluation of several candidate 6-T SRAM bitcell architectures for both high-density and high-speed applications. Based on the electrical evaluations, the chosen cell architectures were incorporated in silicon and verified for their robustness with respect to critical design rules, yields and reliability. The methodology for optical proximity correction for bitcell development has been described here. Minor process enhancements to ensure compatibility of the overall process flow with the SRAM bitcells are described. The use of SRAM-specific electrical test structures serves an important role in validating the electrical performance and confirming the robustness of the bitcells in a manufacturing environment. The monitoring of V/sub ddmin/, the minimum voltage at which the memory is functional was used to drive overall process improvements and reliability. Lastly, measurements of soft error rates demonstrated excellent immunity of the bitcells to single event upsets.

Impact of interconnect process variations on memory performance and design

Interconnect-related effects have become significant factors that can affect complex nanometer designs, such as memories. Thus, a robust memory design methodology needs to include the accurate modeling of interconnect parasitics and interconnect process variations. In this paper we present a statistical design approach to study the impact of interconnect process variations on memory performance and design. This approach uses 3D parasitic extraction, circuit simulation, Monte Carlo and sensitivity analysis to determine the parasitic and performance sensitivities to interconnect process parameter variations for a 90 nm memory design example. The sensitivity analysis results can be used to optimize the memory circuit design and layout to further improve memory performance and robustness.

Design and use of memory-specific test structures to ensure SRAM yield and manufacturability

High-density and high-performance single-port and dual-port SRAM increasingly occupy a majority of the chip area in system-on-chip product designs. Therefore, good yieldability and manufacturability of the SRAM are essential. At the same time there is tremendous competitive pressure to get the best SRAM density and performance. We have previously published and presented the industrys smallest and fastest embedded 6T SRAM bitcells in 0.18 /spl mu/m and 130 nm generation standard CMOS process. We have described how these SRAM bitcells are robust by design even while aggressively driving density and performance. In this paper we discuss the design and use of SRAM-specific test structures that have enabled us to quickly evaluate process-design interactions and to fine-tune process and/or design for improving yields and manufacturability. We have designed test structures using our aggressive production bitcell as basis to probe for any possible weaknesses of the process or design in SRAM Results from these SRAM-specific test structures show good correlation to yield results and in-line SEM observations, and enable us to improve SRAM yields quickly. We have also designed SRAM-transistor test structures to characterize the SRAM cell devices in their real working environment. Results help to evaluate the circuit performance and provide us with guidelines for further design improvements. These data when used in the early stage of the development cycle are also useful for model validation.

A high-performance SRAM technology with reduced chip-level routing congestion for SoC

High-density and high-performance single-port and dual-port SRAM increasingly occupy the majority of the chip area in deep submicron (DSM) system-on-chip (SoC) designs. A complex SoC design may include 10 Mb or more of embedded SRAM and use up to a few hundred individual memory instances with various sizes and configurations. We have previously reported on the need for high-density and high-performance SRAM with good yieldability and manufacturability and our results on 6T-SRAM bitcells in 180 nm and 130 nm generation standard CMOS processes (see Kong, W. et al., 2001; Duan, F. et al., 2003). We have described how these SRAM bitcells are robust by design even while aggressively driving density and performance. We extend the discussion on embedded SRAM bitcell robustness and ease of manufacture to include memory and chip-level considerations, such as memory performance and routing congestion. We present our results on the advantages of using metal 2 bitline bitcells in terms of memory performance, and we highlight the advantages of providing unrestricted, or only partially restricted, routing over memory capability to chip-level routing metallization for minimizing chip-level routing congestion and, hence, improve overall chip area utilization, i.e. chip-level effective density.

Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design

We describe here, the design and use of a unique test chip on power and variability (TPV) to measure and report for the first time, the magnitude of leakage and dynamic power dissipation and its variation. This test chip, fabricated in a state-of-the-art 45nm process node technology, addresses the important issues of variability in power and delay and quantifies them as a function of voltage and cycle time. Multiple power-saving techniques are implemented on-chip to facilitate the analysis. The uniqueness of the chip lies in: a) the use of 64 AES core-based processing-element (PE) blocks that are identical, independently controllable and designed using a state-of-the-art power-aware design flow, b) the use of MTCMOS switches within each PE block combined with multiple power domains which results in excellent granularity of power measurements and, c) the implementation of separate voltage areas in each PE block which enables power measurements down to very low voltages. Good correlation was established between measured data and simulations. Estimates of within-die and die-to-die delay variability were also quantified through measurements of Vddmin, the minimum voltage for functionality. For the silicon tested, the analysis of Vddmin revealed significant within-die variations which were similar in magnitude to the die-to-die variations seen. A methodology to use the Vddmin variation to estimate on-chip delay variability is described in detail.