Suchismita Tewari

Impact of Different Barrier Layers and Indium Content of the Channel on the Analog Performance of InGaAs MOSFETs

A barrier layer in an InGaAs MOSFET, which shows promise for high-performance logic applications due to enhanced electron mobility, is known to further improve the electron mobility. In this paper, a detailed investigation of the impact of different barrier layers on the analog performance of an InGaAs MOSFET is reported for the first time. The device parameters for analog applications, such as transconductance (gm), transconductance-to-drive current ratio (gm/IDS), drain conductance (gd), intrinsic gain (gm/gd), and unity-gain cutoff frequency (fT) are studied with the help of a device simulator. A barrier layer is found to improve the analog performance of such a device in general; with a double-barrier layer showing the best performance. An investigation on the impact of varying the indium content in the channel on the analog performance of an InGaAs MOSFET with a double-barrier layer is also reported in this paper. It is found that a higher In content results in better analog performance of such devices.

Study of InGaAs-Channel MOSFETs for Analog/Mixed-Signal System-on-Chip Applications

MOSFETs with InGaAs in the channel show great promise for high-performance digital applications owing to enhanced electron mobility. In this letter, the analog performance is reported for the first time for an inversion-type enhancement-mode InGaAs-channel MOSFET. With the help of a device simulator, the device parameters for analog applications such as transconductance , transconductance-to-drain-current ratio , drain resistance , intrinsic gain, and unity-gain cutoff frequency are studied for such a device and compared with those for a similarly sized MOSFET. Our results show that InGaAs devices outperform their Si counterparts for analog applications.

Impact of a Spacer Layer on the Analog Performance of Asymmetric InP/InGaAs nMOSFETs

An extensive numerical analysis is performed to study and evaluate the impact of a dielectric sidewall spacer layer on the various device parameters associated with analog circuit performance of In0.75Ga0.25As channel asymmetric nMOSFETs with InP drain at two different channel lengths (Lg) of 20 and 30 nm. The numerical simulation deck is calibrated with asymmetric InGaAs MOSFET experimental characteristics reported in the literature. Our investigations reveal that device parameters such as transconductance gm, transconductance generation factor, and voltage gain Av exhibit significant improvement when a spacer of high dielectric constant k, such as 25, and small length Lsp, such as 5 nm, are used for both Lg = 20 and 30 nm. On the contrary, the output conductance and unity gain cutoff frequency are found to reduce and increase, respectively, with lower k and larger Lsp of the spacer. Our studies suggest that improved analog performance of In-rich asymmetric InGaAs MOSFETs can be achieved by spacer layer engineering at advanced technology nodes.

Investigation on High-Performance CMOS With p-Ge and n-InGaAs MOSFETs for Logic Applications

CMOS circuits built using Ge-channel p-MOSFETs and InGaAs-channel n-MOSFETs have shown promise for high-performance logic applications. In this paper, we investigate for the first time the performance of such circuits using extensive device simulations. The digital performance of a CMOS inverter is evaluated in terms of noise margins, rise time, fall time, and propagation delay. Furthermore, frequency of oscillations of a three-stage ring oscillator is obtained for varying ratio of the channel width of the p- and the n-MOSFETs, respectively (W_p/W_n). Our investigations reveal that the CMOS circuits comprising of p-Ge and n-InGaAs MOSFETs outperform their equally sized Si counterpart. Moreover, superior performance of Ge/InGaAs-based CMOS is obtained for In_0.75Ga_0.25As channel with width ratio (W_p/W_n) of 10: 1. Also, Ge/InGaAs CMOS is found to lose its advantages over Si CMOS for 5 × 10¹² eV^-1 · cm^-2.

Performance of CMOS With Si pMOS and Asymmetric InP/InGaAs nMOS for Analog Circuit Applications

We propose a novel hybrid CMOS comprising a Si-channel pMOSFET and an asymmetric InP/InGaAs nMOSFET in the nanometer regime for analog applications. The performance of such a CMOS is evaluated in terms of voltage gain and gain-bandwidth (GBW) product at two different channel lengths (L_g), 50 and 30 nm, using extensive device simulations. Our investigations reveal that the maximum gain of the hybrid CMOS inverter is improved by 37.5% and 92.1% for asymmetric In_0.75Ga_0.25As nMOS devices with InP drain at L_g = 30 nm for W_p/W_n = 3 and 8, respectively, as compared with an equally sized Si inverter having W_p/W_n = 3. In addition, GBW product of hybrid CMOS (HAS3) comprising asymmetric In_0.75Ga_0.25As nMOSFET with InP source and Si pMOSFET is increased by 148.1% and 260.4% at L_g = 30 and 50 nm, respectively, for W_p/W_n = 3, compared with its Si counterpart. Furthermore, the HAS3 device yields the highest GBW peak, unity current gain frequency, and maximum oscillation frequency as compared with other hybrid and Si CMOS devices at L_g = 30 and 50 nm.

Investigations on the Logic Circuit Behaviour of Hybrid CMOSFETs Comprising InGaAs nMOS and Ge pMOS Devices with Barrier Layers

We investigate the logic circuit behaviour of hybrid CMOS devices made of InGaAs n-channel and Ge p-channel MOSFETs with Si and InP barrier layers, respectively, at channel length L g = 20 and 30 nm. Rise and fall time, noise margin of hybrid CMOS inverters and frequency of oscillations, energy-delay product of 3-stage ring oscillators comprising hybrid CMOS inverters have been investigated to evaluate the performance of the proposed CMOS device. Our findings show a significant amount of reduction of 92.2 and 82.5% for rise and fall time, respectively, in case of proposed hybrid inverter, compared with the corresponding values for equivalent Si CMOS at L g = 30 nm. Oscillation frequency of a 3-stage ring oscillator is found to be 264% higher when compared with its Si counterpart. Also there is an improvement of 17.8 and 77.4% in power-delay and energy-delay product, respectively, for hybrid CMOS inverters in comparison with their equivalent Si counterparts for a channel length of 30 nm. Similar trend is observed in case of channel length of 20 nm.

Effects of channel barrier layer on the analog performance of p-Ge/ n-InGaAs CMOS devices

MOSFETs based on high mobility channel materials such as Ge for p-MOS devices and InGaAs for n-MOS devices have shown promise for future nanoelectronics. Mobility of carriers can further be improved with the incorporation of barrier layer on top of the channel. We report the impact of barrier layer on the analog performance of hybrid CMOS comprising Ge channel p-MOSFET and InGaAs channel n-MOSFET. Our findings show that the InP barrier thickness of 0.7 nm for InGaAs n-MOSFET and the 0.5 nm thick Si barrier in Ge p-MOSFET exhibit strongest carrier confinement within the respective channel. The gain of hybrid CMOS using such barrier thickness exhibits improvement of 150% and 110% at channel length Lg= 30 nm and 20 nm, respectively. Furthermore, our studies reveal that 89.7% and 83% improvement of gain bandwidth product of hybrid CMOS using such barrier thickness at Lg= 30 nm and 20 nm, respectively are observed compared with equivalent Si CMOSFETs.