Abhijit Mallik

Impact of Halo Doping on the Subthreshold Performance of Deep-Submicrometer CMOS Devices and Circuits for Ultralow Power Analog/Mixed-Signal Applications

In addition to its attractiveness for ultralow power applications, analog CMOS circuits based on the subthreshold operation of the devices are known to have significantly higher gain as compared to their superthreshold counterpart. The effects of halo [both double-halo (DH) and single-halo or lateral asymmetric channel (LAC)] doping on the subthreshold analog performance of 100-nm CMOS devices are systematically investigated for the first time with extensive process and device simulations. In the subthreshold region, although the halo doping is found to improve the device performance parameters for analog applications (such as gm/Id, output resistance and intrinsic gain) in general, the improvement is significant in the LAC devices. Low angle of tilt of the halo implant is found to give the best improvement in both the LAC and DH devices. Our results show that the CMOS amplifiers made with the halo implanted devices have higher voltage gain over their conventional counterpart, and a more than 100% improvement in the voltage gain is observed when LAC doping is made on both the p- and n-channel devices of the amplifier

Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications

In this paper, the analog performance is reported for the first time for a double-gate (DG) n-type tunnel field-effect transistor (n-TFET) with a relatively small body thickness (10 nm), which shows good drain current saturation. The device parameters for analog applications, such as transconductance gm, transconductance-to-drive current ratio gm/ID, drain resistance RO, intrinsic gain, and unity-gain cutoff frequency fT, are studied for DG n-TFET, with the help of a device simulator, and compared with that for a similar DG n-MOSFET. Although gm is lower, gm/ID is found to be higher in TFET, except for small values of the gate overdrive voltage, indicating that a TFET can produce higher gain at the same power level than a MOSFET. An extremely high RO and, hence, a high intrinsic gain are also observed for a TFET as compared with that for a MOSFET. A complementary TFET amplifier is found to have more than one order of magnitude higher voltage gain than its MOS counterpart. It is also demonstrated that the drain resistance and, hence, the device gain significantly degrade for increasing body thickness of a TFET.

Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor

A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low- dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (~30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gate-source overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high- spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it.

Drain-Dependence of Tunnel Field-Effect Transistor Characteristics: The Role of the Channel

Because of its different current injection mechanism, a tunnel field-effect transistor (TFET) can achieve a sub-60-m/decade subthreshold swing at room temperature, which makes it very attractive in replacing a metal-oxide semiconductor field-effect transistor, particularly for low-power applications. It is well known that some specific TFET structures show a good drain current ID saturation in the output characteristics, whereas other structures do not. A detailed investigation, through extensive device simulations, of the role of the channel on the drain-potential dependence of double-gate TFET characteristics is presented in this paper for the first time. It is found that a good saturation of ID is observed only for devices in which a thin silicon body is used. A relatively thick silicon body or gate-drain underlaps result in the penetration of the drain electric field through the channel, which does not allow the drain current to saturate, even at higher drain voltages.

Impact of a Spacer–Drain Overlap on the Characteristics of a Silicon Tunnel Field-Effect Transistor Based on Vertical Tunneling

A tunnel field-effect transistor (FET) (TFET), in which the dominant carrier tunneling occurs in a direction that is in line with the gate electric field, shows great promise for sub-0.6-V operation. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer-drain overlap on the device characteristics of such silicon TFET is reported in this paper. It is demonstrated that a supersteep subthreshold swing and a significantly reduced off-state current IOFF can be achieved by appropriate designing of the spacer-drain overlap. An investigation of the influence of the drain potential on the device characteristics reveals that the absence of a tunnel-resistance limited region results in long-channel metal-oxide-semiconductor FET-like output characteristics for such a structure. Short-channel effects, such as drain-induced barrier lowering, are also greatly suppressed in it. Results of the investigation on the scaling properties of such devices are also reported.

The Impact of Fringing Field on the Device Performance of a p-Channel Tunnel Field-Effect Transistor With a High-

Detailed investigation, with the help of extensive device simulations, of the effects of varying the dielectric constant κ of the gate dielectric on the device performance of a p-channel tunnel field-effect transistor (p-TFET) is reported for the first time in this paper. It is observed that the fringing field arising out of a high-κ gate dielectric degrades the device performance of a p-TFET, which is in contrast with its n-channel counterpart of a similar structure, where the same has been reported to yield better performance. The impact of the fringing field is found to be larger for a p-TFET with higher source doping. It is also found that the qualitative nature of the impact of the fringing field does not change with dimension scaling. On the other hand, the higher electric field due to increased oxide capacitance is found to be beneficial for a p-TFET when a high- κ gate dielectric is used in it, as expected. It is also found that a low- κ spacer is beneficial for a p-TFET, similar to that reported for an n-TFET of similar structure.

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A barrier layer in an InGaAs MOSFET, which shows promise for high-performance logic applications due to enhanced electron mobility, is known to further improve the electron mobility. In this paper, a detailed investigation of the impact of different barrier layers on the analog performance of an InGaAs MOSFET is reported for the first time. The device parameters for analog applications, such as transconductance (gm), transconductance-to-drive current ratio (gm/IDS), drain conductance (gd), intrinsic gain (gm/gd), and unity-gain cutoff frequency (fT) are studied with the help of a device simulator. A barrier layer is found to improve the analog performance of such a device in general; with a double-barrier layer showing the best performance. An investigation on the impact of varying the indium content in the channel on the analog performance of an InGaAs MOSFET with a double-barrier layer is also reported in this paper. It is found that a higher In content results in better analog performance of such devices.

Gate Dielectric

MOSFETs with InGaAs in the channel show great promise for high-performance digital applications owing to enhanced electron mobility. In this letter, the analog performance is reported for the first time for an inversion-type enhancement-mode InGaAs-channel MOSFET. With the help of a device simulator, the device parameters for analog applications such as transconductance , transconductance-to-drain-current ratio , drain resistance , intrinsic gain, and unity-gain cutoff frequency are studied for such a device and compared with those for a similarly sized MOSFET. Our results show that InGaAs devices outperform their Si counterparts for analog applications.

Impact of Different Barrier Layers and Indium Content of the Channel on the Analog Performance of InGaAs MOSFETs

It is known that a pocket at the drain end of a Schottky barrier tunneling FET (SB-TFET) helps to improve the device performance in terms of greatly suppressed ambipolar current and reduced drain-induced barrier lowering (DIBL). A detailed investigation, with the help of a numerical device simulator, of the impact of using such a pocket either at the source end or at both the source and the drain ends of an SB-TFET is reported for the first time in this paper. The performance of the above-mentioned two devices is compared with a device having a pocket at the drain end and a conventional MOSFET. Optimization of the barrier height and the pocket parameters is made before performance comparison. It is observed that a pocket at the drain end helps suppress the ambipolar current and reduce both the subthreshold swing and the DIBL. On the other hand, a pocket at the source end helps to improve the ON-state current ION. Using a pocket at both the source and the drain ends results in overall improvement of the device performance. The effects of scaling on such device performance parameters are also reported.

Study of InGaAs-Channel MOSFETs for Analog/Mixed-Signal System-on-Chip Applications

An analytical subthreshold surface potential model for dual-material gate MOSFETs, which considers a varying depth of the channel depletion layer due to the difference in Hatband voltages, and also due to the depletion layers around the source/drain junctions, is presented. The model predictions are compared with the predictions by the 2-D numerical device simulator DESSIS, and a very good agreement between the two is observed.