Sudhanshu Khanna

Flexible Circuits and Architectures for Ultralow Power

Subthreshold digital circuits minimize energy per operation and are thus ideal for ultralow-power (ULP) applications with low performance requirements. However, a large range of ULP applications continue to face performance constraints at certain times that exceed the capabilities of subthreshold operation. In this paper, we give two different examples to show that designing flexibility into ULP systems across the architecture and circuit levels can meet both the ULP requirements and the performance demands. Specifically, we first present a method that expands on ultradynamic voltage scaling (UDVS) to combine multiple supply voltages with component level power switches to provide more efficient operation at any energy-delay point and low overhead switching between points. This system supports operation across the space from maximum performance, when necessary, to minimum energy, when possible. It thus combines the benefits of single-V DD, multi-V DD, and dynamic voltage scaling (DVS) while improving on them all. Second, we propose that reconfigurable subthreshold circuits can increase applicability for ULP embedded systems. Since ULP devices conventionally require custom circuit design but the manufacturing volume for many ULP applications is low, a subthreshold field programmable gate array (FPGA) offers a cost-effective custom solution with hardware flexibility that makes it applicable across a wide range of applications. We describe the design of a subthreshold FPGA to support ULP operation and identify key challenges to this effort.

Sub-threshold circuit design with shrinking CMOS devices

This paper examines the impact of technology scaling to 22nm on sub-threshold circuit design and proposes several solutions for sub-threshold circuits in new processes. To maintain energy-efficient sub-threshold operation, we must reduce variation and suppress leakage current. To combat random variation and minimize energy for nodes below 45nm, we show that special strategies are needed for different categories of sub-threshold circuits.

An 8MHz 75µA/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at V DD =0V with <400ns wakeup and sleep transitions

We demonstrate a non-volatile logic (NVL)-based SoC that backs up its working state (all flip-flops) upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400ns to restore the system state upon power-up. Without NVL, a chip would either have to keep all flip-flops powered resulting in high standby power, or waste energy and time rebooting after power-up. For energy harvesting applications, NVL is a “must have” because there is no constant power source available to keep flip-flops (FFs) alive, and even when the intermittent power source is available, boot-up code alone may consume all of the harvested energy. For handheld devices with limited cooling and battery capacity, zero-leakage ICs with “instant-on” capability are ideal.

An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at

This paper presents a nonvolatile logic (NVL)-based 32-b microcontroller system-on-chip (SoC) that backs up its working state (all flip-flops) upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400 ns to restore the system state upon power-up. Nonvolatile Fe-Cap-based mini-arrays backup the machine state and allow the chip to wake up instantly after a power cycle. Without NVL, a chip would either have to keep all flip-flops powered, resulting in high standby power, or waste energy and time rebooting after power-up. NVL allows systems to use leakier processes to achieve higher performance/lower dynamic power while still having zero leakage in the sleep mode. Optimized system, architecture, and circuit techniques are presented that make NVL practical by adding only 3.6% to the SoC area. Since nonvolatile elements are added to the SoC, reliability and testability have to be key features of the design. This is the first NVL SoC with measured NVL bitcell read signal margin data and extensive test and debug capabilities. The chip is fabricated in a commercial 130-nm low-leakage process and uses a single 1.5-V power supply.

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This paper presents a single inductor energy harvesting and power management (EHM) unit for ultra-low power (ULP) systems. The proposed circuit harvests energy from solar cells from 0.38V input voltage (Vin) and provides 4 output voltages - storage at 5V and VDDs at 3.3V, 1.5V and 1.2V. A peak inductor current control scheme enables high efficiency operation across wide input and output voltage range. The IC supports maximum power point tracking, battery management, and cold starts from 0.38V Vin.

0 V Achieving Zero Leakage With

Ultra low power (ULP) circuits and energy scavenging mechanisms, though conceptually appealing, have been mainly studied in isolation to date. In this paper, we observe energy harvesting prototypes to derive system-level models and to reveal practical issues specific to various types of energy harvesting systems. Our models predict how design decisions affect overall lifetime. We use our model to derive system driven principles for optimizing architecture, voltage selection, and sub-threshold circuit designs across different types of power harvesting systems.

{ 400-ns Wakeup Time for ULP Applications

This paper examines the requirements of wearable sensing applications and their implications for designing the next generation of body area sensors. We define key metrics for wearable sensors and discuss how body area sensors differ from generic wireless sensors. To explore the system level issues with a wearable node, we show measurements from a wearable electrocardiogram (ECG) sensor prototype. Using heart rate monitoring as an example, we show how ultra low power (ULP) circuit design must be applied to support the stringent energy and/or power demands of longlife wearable sensors. Specifically, sub-threshold operation of digital circuits creates opportunities for re-thinking the entire system. We conclude that we can only reach the lower limits of power consumption through cross-hierarchy design of the entire sensor node that leverages ULP digital circuits.

A 1.2µW SIMO energy harvesting and power management unit with constant peak inductor current control achieving 83–92% efficiency across wide input and output voltages

This paper presents a 32 b, 90 nm data flow processor capable of executing arbitrary DSP algorithms using fine grained Dynamic Voltage Scaling (DVS) at the component level with rapid V DD switching and V DD dithering for near-ideal quadratic dynamic energy scaling from 0.25 V-1.2 V. This is the first full processor with Panoptic (all-inclusive) DVS, single clock cycle V DD switching, V DD dithering, and the ability to switch between high performance DVS operation and a sub-threshold mode of operation. This paper also explores V DD header switching and voltage selection considerations for additional savings. Measurements show up to 80% and 43% energy savings of using PDVS over single V DD ( SVDD) and multi- V DD ( MVDD), respectively. Additionally, PDVS shows area savings of up to 65% over MVDD given the same energy consumption.

System design principles combining sub-threshold circuit and architectures with energy scavenging mechanisms

We present a 90nm data flow processor that executes DSP algorithms using fine grained DVS at the component level with rapid V<inf>DD</inf> switching and V<inf>DD</inf> dithering for near-ideal quadratic dynamic energy scaling from 0.25V–1.2V. Measurements show energy savings up to 50% and 46% compared to single-V<inf>DD</inf> and multi-V<inf>DD</inf> alternatives.

Sub-threshold operation and cross-hierarchy design for ultra low power wearable sensors

This paper explores the use of serial circuits for ultra-low-power sub-threshold systems. A serial system leads to a smaller design and higher utilization, yielding 40% active energy, 15x active power, and 32x leakage power benefits. Further, we show that using a serial system in the sub-threshold regime decreases both active energy and leakage power even at the same speed as a parallel system. This is in sharp contrast to strong inversion, where larger bit widths give lower energy and power for the same delay. We identify the unique properties of sub-threshold operation that creates these differences.