Steven Craig Bartling

An 8MHz 75µA/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at V DD =0V with <400ns wakeup and sleep transitions

We demonstrate a non-volatile logic (NVL)-based SoC that backs up its working state (all flip-flops) upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400ns to restore the system state upon power-up. Without NVL, a chip would either have to keep all flip-flops powered resulting in high standby power, or waste energy and time rebooting after power-up. For energy harvesting applications, NVL is a “must have” because there is no constant power source available to keep flip-flops (FFs) alive, and even when the intermittent power source is available, boot-up code alone may consume all of the harvested energy. For handheld devices with limited cooling and battery capacity, zero-leakage ICs with “instant-on” capability are ideal.

An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at

This paper presents a nonvolatile logic (NVL)-based 32-b microcontroller system-on-chip (SoC) that backs up its working state (all flip-flops) upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400 ns to restore the system state upon power-up. Nonvolatile Fe-Cap-based mini-arrays backup the machine state and allow the chip to wake up instantly after a power cycle. Without NVL, a chip would either have to keep all flip-flops powered, resulting in high standby power, or waste energy and time rebooting after power-up. NVL allows systems to use leakier processes to achieve higher performance/lower dynamic power while still having zero leakage in the sleep mode. Optimized system, architecture, and circuit techniques are presented that make NVL practical by adding only 3.6% to the SoC area. Since nonvolatile elements are added to the SoC, reliability and testability have to be key features of the design. This is the first NVL SoC with measured NVL bitcell read signal margin data and extensive test and debug capabilities. The chip is fabricated in a commercial 130-nm low-leakage process and uses a single 1.5-V power supply.

{\rm VDD}=

This paper presents a single inductor energy harvesting and power management (EHM) unit for ultra-low power (ULP) systems. The proposed circuit harvests energy from solar cells from 0.38V input voltage (Vin) and provides 4 output voltages - storage at 5V and VDDs at 3.3V, 1.5V and 1.2V. A peak inductor current control scheme enables high efficiency operation across wide input and output voltage range. The IC supports maximum power point tracking, battery management, and cold starts from 0.38V Vin.

0 V Achieving Zero Leakage With

In the effort to achieve low access energy non-volatile memory, challenges are encountered in sensing data at low power supply voltage. This work presents the design of a ferroelectric random access memory (FRAM) as a promising candidate for this need. The challenges of sensing diminishingly small charge and developing circuits compatible with the scaling of FRAM technology to low voltage and more advanced CMOS nodes are addressed with a time-to-digital sensing scheme. In this work, the 1T1C bitcell signal is analyzed, the circuits for a TDC-based sensing network are presented, and the implementation and operation details of a 1 Mb chip are described. The 1 Mb 1T1C FRAM fabricated in 130 nm CMOS operates from 1.5 V to 1.0 V with corresponding access energy from 19.2 pJ to 9.8 pJ per bit. This approach is generalized to a variety of non-volatile memory technologies.

{ 400-ns Wakeup Time for ULP Applications

Low-power portable electronics such as implantable medical devices require low-access-energy non-volatile memory to deliver longer battery lifetime and richer functionality. Ferroelectric random access memory (FeRAM) technology is a good candidate for both storage [1] and non-volatile RAM [2]. The power and supply voltage of FeRAM need further reduction, and this work presents a solution in anticipation of FeRAM scaling to advanced technology nodes for which the bitcell charge reduces and transistors operate at 1V and below. Specifically, a time-to-digital converter (TDC) sensing scheme is developed to capture the diminishing charge signal from the memory element at low supply voltage.

A 1.2µW SIMO energy harvesting and power management unit with constant peak inductor current control achieving 83–92% efficiency across wide input and output voltages

Catalog ULP microcontrollers (MCUs) have to balance the needs of diverse customers by providing high performance along with near zero standby power and fast wakeup times for real time applications. We present a full HVT 8MHz 75uA/MHz Non-Volatile Logic (NVL) based MCU that has zero standby power and an ultrafast 384ns wakeup time. Non-volatile mini-arrays distributed throughout the logic domain of the MCU snapshot the state of all sequential elements before the MCU goes into a power gated standby mode. Upon wakeup no bootup is required. A high bandwidth parallel connection between the flipflops and mini-arrays helps achieve fast MCU wakeup. NVL has no impact on MCU active mode performance and power and adds only 3.6% to the SoC area. By eliminating leakage in standby mode, NVL allows use of high performance leaky processes in MCU design. We present results from a second generation full SVT 32MHz NVL MCU. The SVT SoC has 4x higher active mode performance or 30% lower active energy than the HVT SoC, but can still achieve zero leakage using NVL.

A Low-Voltage 1 Mb FRAM in 0.13

Microcontrollers (MCUs) serve a central role in the design of IoT leaf nodes. A typical microcontroller comprises of a processing core, program and data memory, serial communication interfaces, general purpose IO (GPIOs) ports, comparators and ADCs, clock generation and power regulators. Microcontrollers have modest clock frequencies and memory capacities, keeping the IC cost low. High level of integration helps improves performance, lowers power and helps achieve a small form factor. All of these are critical in the design of ICs for IoT applications. This chapter focuses on the design of low power microcontrollers using two Texas Instruments (TI) microcontrollers as examples. Both microcontrollers feature embedded Ferro-electric RAM (FRAM) as a low power non-volatile unified data and program memory. Low write power non-volatile memory with high write endurance (number of write cycles) is critical in IoT applications that feature data logging. FRAM has low power writes at 1.5 V, practically unlimited write endurance (>1015), and high yields with millions of shipped parts. In the following sections we describe analog, digital and system design techniques that help achieve the low power metrics in TI microcontrollers.

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In a world where electronics is becoming increasingly ubiquitous, the challenge of powering devices is progressively becoming more difficult. Often it is impractical to replace batteries or line power numerous devices. Energy harvesting is an attractive alternative but has the inherent disadvantage of frequent power loss. For processing systems like microcontrollers (MCUs) power restoration usually requires a boot up sequence before the target application can start. Boot up negatively impacts the power budget and response time of a MCU. This paper describes how non-volatile memory can be used in an efficient manner to preserve the system state of a MCU. As a result, an application can continue operating from where it left off before the power loss, enabling compute through power loss. In contrast to previously published work, this work is a fully integrated SoC that automatically responds to an impending power loss. The MCU features an integrated supply supervisor with fail safe operation. A novel software synchronized state back-up process is also introduced, which drastically reduces the number of flops that need to be saved.

m CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin

In this paper, we describe a fully-integrated digitally-controlled low-dropout regulator (LDO) with dual-loop architecture, providing core voltage to an ultra-low-power microcontroller (MCU). The fine-grained loop dynamically modulates the active-mode LDO drive-strength using the MCU power-modes information for a maximum load current of 6mA, thereby improving the active-mode current efficiency. The coarse-grained loop, enabled to regulate the output voltage only when the MCU enters the standby-mode, ensures ultra-low quiescent current consumption of 500nA, preventing standby drain. A thermometric binary-weighted power-switch matrix improves the transient response figure-of-merit (FOM) by switching between the different power modes. A charge-pump based voltage monitoring circuit is added to allow for wider input voltage range with reduced ripple. Fast digitally-controlled transient response of the LDO allowed the replacement of the (usually off-chip) large capacitor with a high-density on-chip ferroelectric capacitor, thus reducing the LDO sleep-to-active recovery time/energy and allowing full system-on-chip integration. The digitally-controlled LDO, with a wide input voltage range of 1.75-3.3V and nominal output of 1.2V is implemented in a 0.13μm CMOS technology with an active area of 0.034mm2, achieving a FOM of 4.44ps with standby-mode current efficiency of more than 90% for all practical purposes.