Michael Patrick Clinton

A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques

System on Chip (SoC) integration is the theme of the first integrated 3.5G baseband and multimedia applications processor fabricated using a low-power digital and analog design platform and 45nm process technology. This SoC supports mobile standards: HSUPA/HSDPA, WCDMA, EDGE/GPRS/GSM and applications such as MPEG-4 video streaming, Java and MP3 audio. The high- performance multimedia, multiprocessor engine includes an 840MHz ARM1176, a 480MHz TMS320C55x DSP, and a 240MHz image processor.

An 8MHz 75µA/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at V DD =0V with <400ns wakeup and sleep transitions

We demonstrate a non-volatile logic (NVL)-based SoC that backs up its working state (all flip-flops) upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400ns to restore the system state upon power-up. Without NVL, a chip would either have to keep all flip-flops powered resulting in high standby power, or waste energy and time rebooting after power-up. For energy harvesting applications, NVL is a “must have” because there is no constant power source available to keep flip-flops (FFs) alive, and even when the intermittent power source is available, boot-up code alone may consume all of the harvested energy. For handheld devices with limited cooling and battery capacity, zero-leakage ICs with “instant-on” capability are ideal.

An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at

This paper presents a nonvolatile logic (NVL)-based 32-b microcontroller system-on-chip (SoC) that backs up its working state (all flip-flops) upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400 ns to restore the system state upon power-up. Nonvolatile Fe-Cap-based mini-arrays backup the machine state and allow the chip to wake up instantly after a power cycle. Without NVL, a chip would either have to keep all flip-flops powered, resulting in high standby power, or waste energy and time rebooting after power-up. NVL allows systems to use leakier processes to achieve higher performance/lower dynamic power while still having zero leakage in the sleep mode. Optimized system, architecture, and circuit techniques are presented that make NVL practical by adding only 3.6% to the SoC area. Since nonvolatile elements are added to the SoC, reliability and testability have to be key features of the design. This is the first NVL SoC with measured NVL bitcell read signal margin data and extensive test and debug capabilities. The chip is fabricated in a commercial 130-nm low-leakage process and uses a single 1.5-V power supply.

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In the effort to achieve low access energy non-volatile memory, challenges are encountered in sensing data at low power supply voltage. This work presents the design of a ferroelectric random access memory (FRAM) as a promising candidate for this need. The challenges of sensing diminishingly small charge and developing circuits compatible with the scaling of FRAM technology to low voltage and more advanced CMOS nodes are addressed with a time-to-digital sensing scheme. In this work, the 1T1C bitcell signal is analyzed, the circuits for a TDC-based sensing network are presented, and the implementation and operation details of a 1 Mb chip are described. The 1 Mb 1T1C FRAM fabricated in 130 nm CMOS operates from 1.5 V to 1.0 V with corresponding access energy from 19.2 pJ to 9.8 pJ per bit. This approach is generalized to a variety of non-volatile memory technologies.

0 V Achieving Zero Leakage With

Low-power portable electronics such as implantable medical devices require low-access-energy non-volatile memory to deliver longer battery lifetime and richer functionality. Ferroelectric random access memory (FeRAM) technology is a good candidate for both storage [1] and non-volatile RAM [2]. The power and supply voltage of FeRAM need further reduction, and this work presents a solution in anticipation of FeRAM scaling to advanced technology nodes for which the bitcell charge reduces and transistors operate at 1V and below. Specifically, a time-to-digital converter (TDC) sensing scheme is developed to capture the diminishing charge signal from the memory element at low supply voltage.

{ 400-ns Wakeup Time for ULP Applications

Catalog ULP microcontrollers (MCUs) have to balance the needs of diverse customers by providing high performance along with near zero standby power and fast wakeup times for real time applications. We present a full HVT 8MHz 75uA/MHz Non-Volatile Logic (NVL) based MCU that has zero standby power and an ultrafast 384ns wakeup time. Non-volatile mini-arrays distributed throughout the logic domain of the MCU snapshot the state of all sequential elements before the MCU goes into a power gated standby mode. Upon wakeup no bootup is required. A high bandwidth parallel connection between the flipflops and mini-arrays helps achieve fast MCU wakeup. NVL has no impact on MCU active mode performance and power and adds only 3.6% to the SoC area. By eliminating leakage in standby mode, NVL allows use of high performance leaky processes in MCU design. We present results from a second generation full SVT 32MHz NVL MCU. The SVT SoC has 4x higher active mode performance or 30% lower active energy than the HVT SoC, but can still achieve zero leakage using NVL.

A Low-Voltage 1 Mb FRAM in 0.13

In scaled VLSIs, a reliable robust circuit system is essential for the sustainable secure society. The threat to the VLSI system is caused by device, circuit or system issues. This forum provides an overview of the technical challenges as well as recent advances in circuit and system-level reliable VLSI technologies. The forum starts with the overview on the robustness and fault tolerance requirements for microcontrollers in automotive applications. The e-mobility and the new safety norm ISO 26262 affect future requirements on semiconductors. The second talk reviews recent trend of CMOS variability, followed by measured examples on static variations (process) as well as temporal variations (RTN, NBTI). Methods for variability characterization, minimization, and mitigation is also covered. The forum also has three presentations about reliable memory circuits. To enable high-density and low-power SRAMs with robust reliability and fault-tolerance, a variety of energy-efficient, variation-tolerant, and adaptive circuits are reviewed. Embedded non-volatile memory (eNVM) has greatly contributed to the recent growth of MCU market. The current eNVM technologies for highly reliable applications and future directions such as STT-MRAM and ReRAM are presented. The increase of SSD storage capacity drastically increases the total amount of circuits in memory chips inside SSDs. High relaiable SSD controller technologies such as the block device (sector unit Read/Write device) management and the error correcting code are presented. Then, the robust system design is presented. New approaches to thorough test and validation that scale with tremendous growth in complexity and cost-effective tolerance and prediction of failures in hardware during system operation are discussed. The sevnth talk overviews the reliability measures and CMOS failure mechanisms for analog circuits. Simulation techniques to predict performance degradation or device failure is also presented. This forum also highlights the channel coding system which is essential for information transmission and storage. Complex systems for wireless communications require elaborate techniques like iterative (turbo) decoding or advanced algebraic code constructions and decoding algorithms. Finally, the robust energy management is presented for sensor systems and data servers. As a component of energy management, voltage regulators are providing utility beyond power conversion. How voltage regulators play an import role in energy efficient conversion as well as providing information that will help systems manage themselves for maximum utility is discussed.

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This paper will discuss the challenges that continued technology scaling present to circuit designers and how the close interaction between the development of technology, design automation (EDA) tools and the circuit designer can overcome these challenges and enable designs that deliver the benefits customers expect from continued technology scaling.

m CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin

In this paper we present an overview of techniques and methodologies for processor cores and digital SoC integration showing how process sensors, circuitry and system control cooperate in order to achieve the best power, performance, area and yield trade-off. We cover combinatorial and sequential logic as well as memory cores in the context of retention, power gating and adaptive features. Various techniques are also given as example and illustrated by silicon measurements.