Sudhir K. Madan

A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process

A low-voltage (1.3 V) 64-Mb ferroelectric random access memory (FRAM) using a one-transistor one-capacitor (1T1C) cell has been fabricated using a state-of-the-art 130-nm transistor and a five-level Cu/flouro-silicate glass (FSG) interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate-oxide low-voltage logic process. Novel overwrite sense amplifier and programmable ferroelectric reference generation schemes are employed for fast reliable read-write cycle operation. Address access time for the memory is less than 30 ns while consuming less than 0.8 mW/MHz at 1.37 V. An embedded FRAM (eFRAM) density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/.

A 64 Mbit embedded FeRAM utilizing a 130 nm, 5LM Cu/FSG logic process

A low-voltage (1.3V), 64 Mbit Ferroelectric Random Access Memory using a 1-transistor, 1-capacitor (1T1C) cell is demonstrated. This is the largest FRAM memory demonstrated to date. The memory is constructed using a state-of-the-art 130 nm transistor and a five-level Cu/FSG interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate oxide, low-voltage logic process. Address access time for the memory is less than 30 ns while consuming 0.57 mW/MHz at 1.37 V. An eFRAM density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/.

Low-power ferroelectric random access memory embedded in 180nm analog friendly CMOS technology

An embedded 448kb 2T-2C FRAM, integrated into a 180nm analog process flow, has been developed and qualified for more than 10years data retention at 125°C. Key electrical characteristics of the memory include wide signal margins with no outlier bits, high endurance write/read cycling (>>1015 cycles), stable retention (>>10yrs at 125°C), and extremely low bit error rate following 260°C Pb-free solder board-attach reflow. Results suggest that the technology can find wide use in applications ranging from consumer electronics to automotive where highly reliable embedded memory and analog components are required.

An 8Mb 1T1C ferroelectric memory with zero cancellation and micro-granularity redundancy

New design techniques facilitate a high reliability 1T1C 8Mb ferroelectric random access memory with 0.71u2 cell operating at 1.5V on a 130nm 5LM Cu process. Zero cancellation increases the cell interrogation voltage by using a nonswitching ferroelectric capacitor to remove charge from the bit line that compensates the linear charge from the cell capacitor. A micro-granularity redundancy approach preserves high repair probability for up to 128 single bit failures. Trim data is stored in 2T2C configuration rows for redundancy, reference, regulator and control logic adjustment

180nm FRAM reliability demonstration with ten years data retention at 125°C

Reliability of a 2T-2C, 448kbit FRAM embedded within 180nm CMOS is presented. The results indicate a 10-year, 125°C data retention capability for this technology. Further, sufficient signal margin remains for sensing following 260°C Pb-free solder reflow step demonstrating that code data can be stored through the board-attach process. A new margin test approach, which enables depolarization effects to be quantified, has been developed. A model to estimate device fail rate based on array size, word length, error correction circuitry and bit error rate is also described.

Reliability Demonstration of a Ferroelectric Random Access Memory Embedded within a 130nm CMOS Process

Reliable operation of a 4 Mb ferroelectric random access memory (FRAM) embedded within a standard 130 nm CMOS process is demonstrated. Intrinsic endurance test to 5.4×1012 cycles shows no degradation of switched polarization. 10 year, 85degC, data retention life is demonstrated with 125°C data bake to 1,000 Hrs with no fails.

Reliability characterization of a Ferroelectric Random Access Memory embedded within 130nm CMOS

Reliability data is presented for a 4Mb Ferroelectric Random Access Memory (F-RAM) embedded within a 130nm CMOS process. Write/read endurance in the device exhibits stable intrinsic bit properties through 2.7x1013 cycles. Data retention demonstrates 10 year, 85°C operating life. No fails were observed with full-chip endurance test to 108 cycles followed by 1,000 hours of data retention bake at 125°C. Robust process reliability is demonstrated with no fails at 125°C operating life test.

High-Density 8Mb 1T-1C Ferroelectric Random Access Memory Embedded Within a Low-Power 130nm Logic Process

Ferroelectric memories are the most promising alternative to traditional embedded nonvolatile memories, such as flash and EEPROMs, because of their fast read/write cycle time, non-volatile data retention, low voltage/low power operation and low number of additional masks for fabrication (+2). An embedded ferroelectric memory (FRAM) has been developed using a 1.5 V, 130 nm 5 metal layer Cu/FSG logic process. The only modification to the logic process was the addition of a ferroelectric process module consisting of two additional masks (FECAP, VIAO) immediately before MET1. The ferroelectric was 70 nm Pb(Zr,Ti)O3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The electrical properties of a 8 Mb 1T-1C embedded FRAM were characterized. This eFRAM process has been used to simultaneously fabricate a digital signal processor (DSP) using the eFRAM process flow and the operating frequency is nearly the same relative to the CMOS baseline. This eFRAM process flow creates a technology platform that enables ultra-low-power devices.

DRAM plate electrode bias optimization for reducing leakage current in UV-O/sub 3/ and O/sub 2/ annealed CVD deposited Ta/sub 2/O/sub 5/ dielectric films

A new plate biasing scheme is described which allowed the use of 65% higher supply voltage without increasing the leakage current for the UV-O/sub 3/ and O/sub 2/ annealed chemical-vapor-deposited tantalum pentaoxide dielectric film capacitors in stacked DRAM cells. Dielectric leakage was reduced by biasing the capacitor plate electrode to a voltage lower than the conventionally used value of V/sub cc//2. Ta/sub 2/O/sub 5/ films with 3.9 nm effective gate oxide, 8.5 fF//spl mu/m/sup 2/ capacitance and >

Extraction of channel length and junction voltage in n/sup +//n/n/sup +/ or n/sup +//p/n/sup +/ polysilicon resistors

A method for extraction of channel length and junction voltage of poly-Si resistors is presented. Direct extraction of channel length can be performed for n/sup +//n/n/sup +/ resistors operating in the nonlinear I-V regime. However, poly-Si resistors may have channel doping opposite to that of the source/drain doping. For this case, a method is presented for extraction of the current-dependent voltage drop across the drain n/sup +//p junction. Importantly, this junction voltage drop can be an appreciable fraction of the drain-to-source bias and thus is important for correct analysis of n/sup +//p/n/sup +/ resistors. >