Kezhakkedath R. Udayakumar

Reliability properties of low-voltage ferroelectric capacitors and memory arrays

We report on the reliability properties of ferroelectric capacitors and memory arrays embedded in a 130-nm CMOS logic process with 5LM Cu/FSG. Low voltage (<1.5 V) operation is enabled by the 70-nm thick MOCVD PZT ferroelectric films. Data loss resulting from high temperature bakes is primarily caused by the imprint effect, which shows /spl sim/1.5 eV time-to-fail activation energy. Excellent bit endurance properties are observed on fully packaged memory arrays, with no degradation up to 10/sup 13/ write/read polarization switching cycles. Retention measured after 10/sup 12/ switching cycles demonstrates no degradation relative to arrays with minimal cycling.

Stoichiometry and phase purity of Pb(Zr,Ti)O3 thin films deposited by metal organic chemical vapor deposition

(Pb,Zr)TiO3 (PZT) films have been prepared by metal organic chemical vapor deposition on 200mm wafers. Phase pure perovskite films were deposited in a self-correcting region where the Pb stoichiometry is relatively insensitive to increasing Pb content in the gas phase. Films deposited with Pb flows lower than those used in the self-correcting region showed second phase ZrO2 whereas films deposited at Pb flows higher than those used in the self-correcting region showed second phase PbO. The PZT grains are columnar, extending from the bottom electrode to the top electrode. In the self-correcting region, PZT films of 70nm nominal thickness show good ferroelectric behavior with switched polarization of ∼40μC∕cm2 at 1.5V and saturation voltage of ∼1.2V. The films have an average roughness of ∼4nm with grain size of ∼700A. The impact of the deposition parameters such as deposition temperature, pressure, precursor flow, and oxygen flow during deposition on the self-correcting region was investigated. Increasing ...

Low-power ferroelectric random access memory embedded in 180nm analog friendly CMOS technology

An embedded 448kb 2T-2C FRAM, integrated into a 180nm analog process flow, has been developed and qualified for more than 10years data retention at 125°C. Key electrical characteristics of the memory include wide signal margins with no outlier bits, high endurance write/read cycling (>>1015 cycles), stable retention (>>10yrs at 125°C), and extremely low bit error rate following 260°C Pb-free solder board-attach reflow. Results suggest that the technology can find wide use in applications ranging from consumer electronics to automotive where highly reliable embedded memory and analog components are required.

Reliability of Ferroelectric Random Access memory embedded within 130nm CMOS

We present results of a comprehensive reliability evaluation of a 2T–2C, 4Mb, Ferroelectric Random Access Memory embedded within a standard 130nm, 5LM Cu CMOS platform. Wear-out free endurance to 5.4×1013 cycles and data retention equivalent of 10 years at 85°C is demonstrated. The results show that the technology can be used in a wide range of applications including embedded processing.

Embedded ferroelectric memory using a 130-nm 5 metal layer Cu / FSG logic process

An embedded ferroelectric memory (FRAM) has been developed using a 1.5V, 130nm 5 metal layer Cu / FSG logic process. The only modification to the logic process was the addition of a ferroelectric process consisting of two additional masks (FECAP, VIA0) immediately before MET1. The ferroelectric was 70nm Pb(Zr,Ti)O3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The bit distribution of small ferroelectric capacitors (< 0.2 /spl mu/m/sup 2/) was measured after fabrication and bake. A reasonable amount of property degradation after 6000hr 125/spl deg/C bake was observed.

180nm FRAM reliability demonstration with ten years data retention at 125°C

Reliability of a 2T-2C, 448kbit FRAM embedded within 180nm CMOS is presented. The results indicate a 10-year, 125°C data retention capability for this technology. Further, sufficient signal margin remains for sensing following 260°C Pb-free solder reflow step demonstrating that code data can be stored through the board-attach process. A new margin test approach, which enables depolarization effects to be quantified, has been developed. A model to estimate device fail rate based on array size, word length, error correction circuitry and bit error rate is also described.

Reliability Demonstration of a Ferroelectric Random Access Memory Embedded within a 130nm CMOS Process

Reliable operation of a 4 Mb ferroelectric random access memory (FRAM) embedded within a standard 130 nm CMOS process is demonstrated. Intrinsic endurance test to 5.4×1012 cycles shows no degradation of switched polarization. 10 year, 85degC, data retention life is demonstrated with 125°C data bake to 1,000 Hrs with no fails.

Plasma Etch Processes for Embedded FRAM Integration

We describe the etch processes used for integration of embedded ferroelectric random access memory (FRAM) within a standard CMOS logic flow. The ferroelectric module is inserted following front-end contact formation and prior to backend integration using only two additional mask levels: capacitor pattern and bi-level via pattern. The single-mask stack etch process employs a TiAlN hardmask to define Ir/IrOx/PZT/IrOx/Ir capacitors. Protective sidewalls can be formed using an etchback process. The bi-level via etch and subsequent metal fill processes complete the FRAM module formation. Functional 4 MB arrays embedded with 5 levels of Cu/FSG integration have been demonstrated.

Reliability characterization of a Ferroelectric Random Access Memory embedded within 130nm CMOS

Reliability data is presented for a 4Mb Ferroelectric Random Access Memory (F-RAM) embedded within a 130nm CMOS process. Write/read endurance in the device exhibits stable intrinsic bit properties through 2.7x1013 cycles. Data retention demonstrates 10 year, 85°C operating life. No fails were observed with full-chip endurance test to 108 cycles followed by 1,000 hours of data retention bake at 125°C. Robust process reliability is demonstrated with no fails at 125°C operating life test.

High-Density 8Mb 1T-1C Ferroelectric Random Access Memory Embedded Within a Low-Power 130nm Logic Process

Ferroelectric memories are the most promising alternative to traditional embedded nonvolatile memories, such as flash and EEPROMs, because of their fast read/write cycle time, non-volatile data retention, low voltage/low power operation and low number of additional masks for fabrication (+2). An embedded ferroelectric memory (FRAM) has been developed using a 1.5 V, 130 nm 5 metal layer Cu/FSG logic process. The only modification to the logic process was the addition of a ferroelectric process module consisting of two additional masks (FECAP, VIAO) immediately before MET1. The ferroelectric was 70 nm Pb(Zr,Ti)O3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The electrical properties of a 8 Mb 1T-1C embedded FRAM were characterized. This eFRAM process has been used to simultaneously fabricate a digital signal processor (DSP) using the eFRAM process flow and the operating frequency is nearly the same relative to the CMOS baseline. This eFRAM process flow creates a technology platform that enables ultra-low-power devices.