Suk-hui Lee

Design of high gain amplifier using on-chip transformer by neutralization

A high frequency and high gain amplifier using standard 65 nm TSMC technology is presented in this paper. A gain of the proposed amplifier was boosted by inserting on-chip transformer which inverts amplifiers output phase to neutralize gain limiting parasitic capacitors. To control stability issue of the transformer induced positive feedback amplifier under the environments of process variations, variable neutralizer capacitors with variable capacitor value by body node biasing are suggested. The theory, simulation and measurement are shown in this paper. An implementation prototype is evaluated using on-wafer proving. The amplifier showed peak gain of 30 dB and noise figure of 4.6 dB under 8.9 mW power consumption with 1V power supply condition. The measured IIP3 was -26 dBm.

A design of tunable component for font end module

This paper describes VCO designs based on varactor tuned architecture. The oscillators of FMCW generator have been designed in a 0.13μm SiGe BiCMOS technology, thus targeting automotive Radar and millimeter-wave applications. Their tuning ranges are 2.98 GHz. The VCO chip achieve low phase noise characteristics -102.68 dBc/Hz at 1 MHz offset from the tunable frequency.

The design of low power high gain transformer feedback amplifier

In this paper, we present a low power consumption and high gain low noise amplifier using transformer feedback to neutralize the gate-source overlap capacitance of a FET. It is a single-ended amplifier designed in 65nm CMOS technology for 60 GHz transceiver. This LNA achieves a simulated gain of 10.46 dB, noise figure of 3.216 dB at 60 GHz.

The design of high gain amplifier with transformer feedback combination

In this paper, we present a low power consumption and high gain low noise amplifier using transformer feedback to neutralize the gate-source and gate-drain overlap capacitance of a FET. It is a single-ended amplifier designed in 65nm CMOS technology for 60 GHz transceiver. This LNA achieves a simulated gain of 10.64 dB, noise figure of 3.10 dB at 60 GHz.

Thermal memory effect modeling and compensation for GaN Doherty amplifier

This paper reports on an attempt to investigate, model and quantity the contribution of the electrical nonlinearity effects and the thermal memory effects to a Doherty amplifiers distortion generation and suggests thermal memory effect compensator for pre-distorter. Also this paper reports on the development of advanced Doherty amplifier structure with limiter and linear amplifier. A compensated LLHD amplifier enhances ACLR performance about 22 dB.