Ki-Jin Kim

High Isolation Internal Dual-Band Planar Inverted-F Antenna Diversity System with Band-Notched Slots for MIMO Terminals

Internal dual-band planar inverted-F antenna (PIFA) diversity system for portable devices, operating in the 2.4-GHz band (2400-2484MHz) and 5.2-GHz band (5150-5350MHz), is presented. To reduce the mutual coupling and get the high isolation between the two internal dual-band antennas, we proposed the band-notched lambda/4 slots on the ground plane. The optimized band-notched slots for high isolation, high radiation efficiency and high effective diversity gain are analyzed. The band-notched slots can be used to the small MIMO terminals which require high isolation between antennas

A 60 GHz Wideband Phased-Array LNA With Short-Stub Passive Vector Generator

This letter presents 60 GHz 5 b phased-array low noise amplifier (LNA) implemented in 90 nm CMOS for a short range wireless application. The design consists of common source two-stage LNA, short-stub vector generator, I/Q modulator with 5 b digital to analog converter and differential to single amplifier. All the proposed amplifiers are designed using a transformer coupled method which results in wideband operation to meet the frequency requirement of the standard. The proposed circuit provides 360 phase controllability over 50-70 GHz band while achieving 12.5 dB gain, 6.55 dB NF and consuming 50 mA from 1.2 V. The measured rms phase error is in the phase accuracy limitation (differential phase array) and gain variation is quite low (<; 0.92 dB) over 5 b control range.

An 880 / 1760 MHz tunable bandwidth active RC low-pass filter using high gain amplifier

For 60GHz unlicensed applications, an analog base-band filter using an active RC type is presented. An 880 / 1760 MHz tunable bandwidth third order Butterworth low-pass filter using high gain amplifiers is fabricated in 90nm standard CMOS process. Drawing 29.2 mW from 1.2 V power supply, the low frequency gains of the filter are -1.2 and -2.5 dB, and the output third order intercept points (OIP3) are +2.85 and +2.35 dBm for the single channel and channel bonding conditions, respectively.

A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs

A background timing-mismatch calibration algorithm is proposed, which detects and corrects the sampling time mismatches in time-interleaved analog-to-digital converter (ADC) channels by analyzing the sign-equality of a reference slope and a timing-mismatch-induced error value. The sign of the ideal derivative along the input is estimated through the adjacent channel outputs, thus not requiring an additional time-shifted ADC channel. The sign of the reference slope, which is the estimated sign of the ideal derivative at the sampling edge of the reference ADC, is matched against the sign of the error value to determine if the timing mismatch is leading or lagging the sampling edge of the reference ADC. The proposed algorithm aligns the sampling edge of each subchannel to that of the reference ADC by handling only two sign bits and thus reduces the timing mismatches with only negligible hardware overhead consisting of simple logic gates.

Design of high gain amplifier using on-chip transformer by neutralization

A high frequency and high gain amplifier using standard 65 nm TSMC technology is presented in this paper. A gain of the proposed amplifier was boosted by inserting on-chip transformer which inverts amplifiers output phase to neutralize gain limiting parasitic capacitors. To control stability issue of the transformer induced positive feedback amplifier under the environments of process variations, variable neutralizer capacitors with variable capacitor value by body node biasing are suggested. The theory, simulation and measurement are shown in this paper. An implementation prototype is evaluated using on-wafer proving. The amplifier showed peak gain of 30 dB and noise figure of 4.6 dB under 8.9 mW power consumption with 1V power supply condition. The measured IIP3 was -26 dBm.

Ternary-level thermometer C-DAC switching scheme for flash-assisted SAR ADCs

A ternary-level thermometer capacitive digital-to-analog converter (C-DAC) switching scheme is proposed for flash-assisted successive-approximation register (FA-SAR) analog-to-digital converters (ADCs). By minimizing the capacitor reference switching operations of the C-DAC with the help of thermometer codes readily available from the assistant flash ADC, integral nonlinearity (INL) and differential nonlinearity (DNL), as well as C-DAC switching energy, are significantly improved from conventional switching schemes, which in turn makes near thermal-noise-limited capacitor designs feasible without complex capacitor weight calibrations.

A design of tunable component for font end module

This paper describes VCO designs based on varactor tuned architecture. The oscillators of FMCW generator have been designed in a 0.13μm SiGe BiCMOS technology, thus targeting automotive Radar and millimeter-wave applications. Their tuning ranges are 2.98 GHz. The VCO chip achieve low phase noise characteristics -102.68 dBc/Hz at 1 MHz offset from the tunable frequency.

The design of low power high gain transformer feedback amplifier

In this paper, we present a low power consumption and high gain low noise amplifier using transformer feedback to neutralize the gate-source overlap capacitance of a FET. It is a single-ended amplifier designed in 65nm CMOS technology for 60 GHz transceiver. This LNA achieves a simulated gain of 10.46 dB, noise figure of 3.216 dB at 60 GHz.

The design of high gain amplifier with transformer feedback combination

In this paper, we present a low power consumption and high gain low noise amplifier using transformer feedback to neutralize the gate-source and gate-drain overlap capacitance of a FET. It is a single-ended amplifier designed in 65nm CMOS technology for 60 GHz transceiver. This LNA achieves a simulated gain of 10.64 dB, noise figure of 3.10 dB at 60 GHz.

Design of 60 GHz low power & high data rate receiver for the next generation NFC systems

This paper suggests 60 GHz non-coherent OOK receiver which is a strong candidate for 5G near filed communications in Korea. The receiver consists of a fully differential envelop detector and a limiting amplifier. The measured receiver shows 32 dB peak gain at -28 dBm input power level. The sensitivity of the receiver is measured -25 dBm under 3 Gbps data rate. The proposed receiver is fabricated with 65nm CMOS process and its measured power consumption is only 4.3 mW. As a result, the proposed receiver achieves energy efficiency of 1.43 pJ/bit.