Sukeshwar Kannan

Device performance analysis on 20nm technology thin wafers in a 3D package

This paper presents the impact of wafer thinning process on GLOBALFOUNDRIES high-k metal gate CMOS wafers with TSV. The initial study of wafer backside surface finish and thickness was performed on non-TSV wafers, and the impact on active devices such as: MOS (metal-oxide semiconductor) capacitors, ring oscillators, analog circuit performance and front end of line (FEOL) reliability macros was characterized. Based on the experimental results, a suitable wafer surface finish and thickness was selected for TSV wafer processing. The impact of wafer thinning on device performance was monitored at various stages of packaging, including before thinning, after thinning, end-of line (EOL), and post package reliability tests.

TSV integration on 20nm logic Si: 3D assembly and reliability results

Each new technology node brings new design and technology challenges making it harder to maintain Moores law in a cost effective way. Maintaining cost effectiveness is becoming a major challenge for IDMs, fabless companies and foundries. 3D/2.5D technologies offer some unique advantages over traditional scaling such as higher power efficiency, higher bandwidth and heterogeneous integration which can arguably lower design complexity and manufacturing cost. While advantages of 3D ICs are well known, adoption of this technology has been shifting out due to several technological challenges and manufacturing supply chain concerns. In this paper, 3D packages are realized by stacking mechanical Wide IO memory onto a 20nm low power mobile logic die with through silicon vias (TSVs). This architecture is very promising for mobile application as it can provide lower power consumption, higher bandwidth and faster communication between memory and logic with a smaller form factor. Various technical challenges that were addressed while building a 3D package along with its process and reliability results, both wafer level and package level, are discussed in this paper.

Challenges to via middle TSV integration at sub-28nm nodes

This work presents the via middle TSV integration at sub-28 nm nodes using a new local interconnect scheme involving V0 vias. Various V0 schemes are presented along with their respective resistance, capacitance and leakage current data. The characterization and reliability results are presented through TSV daisy chain structures and MOL via chains.

Pre-bond testing of the silicon interposer in 2.5D ICs

In interposer-based 2.5D integrated circuits, the passive silicon interposer is the least expensive component in the chip. Thus, it is desirable to test the interposer before bonding to ensure that more expensive and defect-free dies are not stacked on a faulty interposer. We present an efficient method to locate defects in a passive interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. In order to reduce test time, the concept of weighted critical area is defined and utilized. We present HSPICE simulation results to demonstrate the effectiveness of the pre-bond test solution. The benefit of using weighted critical area is demonstrated using a commercial interposer from GLOBALFOUNDRIES.

Prebond Testing and Test-Path Design for the Silicon Interposer in 2.5-D ICs

In interposer-based 2.5-D integrated circuits, the passive silicon interposer is the least expensive component in the chip. Thus, it is desirable to test the interposer before bonding to ensure that more expensive and defect-free dies are not stacked on a faulty interposer. We present an efficient method to locate defects in a passive interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. Moreover, the concept of weighted critical area is defined and utilized to reduce test time. In order to fully determine the location of each e-fuse and the order of functional interconnects in a test path, we also present a test-path design algorithm. The proposed algorithm can generate all test paths for interconnect testing. We present HSPICE simulation results to demonstrate the effectiveness of the prebond test solution. Test-path designs are also presented to highlight the efficiency of the test-path design algorithm. The benefit of using weighted critical area is demonstrated using a commercial interposer from industry.

Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits

Monolithic three-dimensional (M3D) integration is gaining momentum, as it has the potential to achieve significantly higher device density compared to 3D integration based on through-silicon vias. M3D integration uses several techniques that are not used in the fabrication of conventional integrated circuits (ICs). Therefore, a detailed analysis of the M3D fabrication process is required to understand the impact of defects that are likely to occur during chip fabrication. In this article, we first analyze electrostatic coupling in M3D ICs, which arises due to the aggressive scaling of the interlayer dielectric (ILD) thickness. We then analyze defects that arise due to voids created during wafer bonding, a key step in most M3D fabrication processes. We quantify the impact of these defects on the threshold voltage of a top-layer transistor in an M3D IC. We also show that wafer-bonding defects can lead to a change in the resistance of interlayer vias (ILVs), and in some cases lead to an open in an ILV or a short between two ILVs. We then analyze the impact of these defects on path delays using HSpice simulations. We study their impact on the effectiveness of delay-test patterns for multiple instances of IWLS 2005 benchmarks in which these defects were randomly injected. Our results show that the timing characteristics of an M3D IC can be significantly altered due to coupling and wafer-bonding defects if the thickness of its ILD is less than 100nm. Therefore, for such M3D ICs, test-generation methods must be enhanced to take M3D fabrication defects into account.

Impact of TSV integration on 14nm FinFET device performance

The integration of Through-Silicon Vias (TSVs) in CMOS wafers has the potential to cause performance shifts of devices in close proximity due to mobility change caused by mechanical stress. To ensure successful integration of TSV into a baseline technology, these shifts must be negligible to allow seamless integration of TSVs into circuit designs. As the first publication of its kind by an advanced node foundry, this paper presents results of a study to analyze TSV impact on 14nm FinFET device and analog circuit performance. These include n or p type short and long channel FETs, current mirrors, and operational amplifiers (op-amp). The unique TSV capture pad structure used by GLOBALFOUNDRIES for advanced node TSV integration is discussed. This structure allows for improved TSV middle integration yield and ensures that a good electrical connection from the back-end of line (BEOL) to the TSV is formed. A physical property analysis was also done on the TSV structure to determine capacitance, leakage, and dielectric liner breakdown voltage. Finally, a full suite of characterization measurements were performed on the 14nm FinFET thin wafers to assess the impact of the wafer thinning process on front-end of line (FEOL) devices.

Impact of wafer-bonding defects on Monolithic 3D integrated circuits

Monolithic three-dimensional (M3D) integration has the potential to achieve significantly higher device density compared to 3D integration based on through-silicon vias. We analyze defects that arise due to voids created during the wafer-bonding step in M3D integration. We quantify the impact of these defects on the threshold voltage of a top-layer transistor in an M3D integrated circuit. We also show that wafer-bonding defects can lead to a change in the resistance of inter-layer vias (ILVs), and in some cases, lead to an open in an ILV or a short between two ILVs. We then analyze the impact of these defects on path delays. Our results show that the timing characteristics of an M3D IC can be significantly altered due to the presence of wafer-bonding defects.

Impact of TSV process on 14nm FEOL and BEOL reliability

This paper presents the impact of Through Silicon Via (TSV) process on wafer level reliability with respect to front-end of line (FEOL) and back-end of line (BEOL) reliability aspects. A TSV proximity study was performed by placing the TSV at various keep-out zone (KOZ) distances and different orientations of horizontal, vertical, and 45 degrees. FEOL and BEOL test structures were designed using stand-alone devices having TSV at KOZ distance of 2μm, 3μm, 5μm and 7μm and different orientations. Reliability tests show no impact on TSV KOZ on both FEOL and BEOL device performance. Additionally, we also performed a thinning study on the TSV wafers to characterize the impact of the wafer thinning process. We observed negligible difference between pre-thinning and post-thinning measurements and they fall within the expected wafer-to-wafer and lot-to-lot variability of the 14nm baseline process. As part of our ongoing reliability qualification for 14nm TSV reliability tests is currently being performed on these thin wafers.

SoC Speed Binning Using Machine Learning and On-Chip Slack Sensors

Speed binning of system-on-chips (SoCs) using conventional