Ramakanth Alapati

Novel stress-free Keep Out Zone process development for via middle TSV in 20nm planar CMOS technology

For the first time, a near-Zero Keep Out Zone TSV capability is demonstrated utilizing the Middle Of Line (MoL) layer stack process development and optimization. This is MoL layer stack consisted of a nitride, PMD oxide, and contact protection layer. Careful selection of a high CTE Contact Protection layer to compensate the TSV induced stress in Silicon (Silicon CTE is 2.3 ppm/°C) yields the near-Zero Keep Out Zone, confirmed with silicon measurement data.

Through-Silicon Vias: Drivers, Performance, and Innovations

To address the abating performance improvements from device scaling, innovative 2.5-D and 3-D integrated circuits with vertical interconnects called through-silicon vias (TSVs) have been widely explored. This paper reviews TSVs with focus on the following: 1) key drivers for TSV-based integration; 2) TSV fabrication techniques; 3) TSV electrical and thermomechanical performance fundamentals and characterization techniques; and 4) novel technologies to attain enhanced performance beyond the state-of-the-art TSVs.

Challenges to via middle TSV integration at sub-28nm nodes

This work presents the via middle TSV integration at sub-28 nm nodes using a new local interconnect scheme involving V0 vias. Various V0 schemes are presented along with their respective resistance, capacitance and leakage current data. The characterization and reliability results are presented through TSV daisy chain structures and MOL via chains.

Challenges of analog and I/O scaling in 10nm SoC technology and beyond

Continuous process-level and system-level innovation has driven Moores Law scaling for the last fifty years, and will continue to do so in the next decades. In the last two decades, there has been an acceleration of new materials and devices into semiconductor manufacturing, such as low-k, strained Si, high-k, and FinFET, in order to continue process and cost scaling. At the same time, ever increasing component integration on SoCs has further driven cost scaling, allowing the current mobile era to take shape. In the next decade, the focus of SoC innovation will be on patterning and low-resistance materials on the process side, and multi-die package integration on the system side.

New interferometric measurement technique for small diameter TSV

High aspect ratio through silicon vias (TSV) present a challenge for measurement of bottom critical dimension (BCD) and depth. TSVs smaller than 5 micron diameter with greater than 12:1 depth to BCD aspect ratio have particularly poor signal to noise ratio in the measured signal. This paper proposes a method for improving the interferometric measurement of these very small and high-aspect ratio TSVs with data showing the feasibility of measuring both BCD and depth of 19:1 aspect ratio TSVs. This work demonstrates the capability to analyze the scanning white-light interferometry (SWLI) signal for such high aspect ratio TSV BCD and depth measurements with >0.95 R2 correlation to reference metrology obtained through cross section SEM. Precision of within 2.5% of nominal BCD and within 0.1% of nominal depth was demonstrated for 10x repeatability measurements.

Impact of wafer thinning on High-K Metal Gate 20nm devices

In this paper, the impact of wafer thinning on 20nm High K Metal Gate (HKMG) technology is evaluated. Fully fabricated test wafers are thinned down to well below 100μm, into the range required for 3D integration. The impact on NMOS and PMOS device performance parameters; channel current and threshold voltage (Vt) is investigated. Device reliability is monitored using NBTI (negative bias temperature instability) measurements. It is found that wafer thinning has negligible impact on Vt of I/O devices. However, we have seen a small impact on the channel leakage, and a moderate impact on saturation currents of high performance core devices. The channel current is reduced ~5% for NMOS, while there is a ~10% enhancement in the PMOS device. Device reliability was assessed using NBTI and no degradation is seen on the devices. This confirms that the thinning did not impact the front end of line gate oxide integrity.

TSV integration with 20nm CMOS technology for 3D-IC enablement

This paper describes the process development of TSV integration with 20nm CMOS technology and device performance characterization for 3D integrated circuit (3DIC) enablement. 6×55um Through-silicon-via (TSV) on 20nm CMOS technology has been developed and demonstrated. Key module process issues, such as V0 high resistance, M1 high leakage and Cu pumping which prevent TSV to be integrated with BEOL through via-middle approach for mobile applications, have been addressed through design of experiments (DOEs) study and process optimization. TSV electrical characterization, TSVs impact on transistor, analog/digital circuits & BEOL performance considering TSV Keep-out-zone (KOZ) & Cu pumping impact have been intensively investigated and presented in this paper. Cu diffusion & contamination during TSV back side integration, i.e. MEOL process, has also been analyzed and monitored with time of flight-secondary ion mass spectrometry (TOF-SIMs) evaluation. Electrical test results confirm that the optimized process is robust and minimizes the impact of TSV KOZ and Cu pumping on device and BEOL interconnects.

Correlation study of white light interferometer measurements with atomic force microscope measurements for post-CMP dishing measurements applied to TSV processing

White light interferometry (WLI) has been used in the semiconductor industry for the measurement of topography, step height, and via depth, utilizing its fundamentally short coherence length. This allows the tool to achieve nanometer level resolution, making this technique ideal for through silicon via (TSV) measurements for high aspect ratio vias. In this paper, we will discuss one of the important measurement steps within 20 nm/14 nm technology node TSV processing, and how WLI is applied to make the measurements. For the post-chemical mechanical polish (CMP) dishing measurement near TSVs, we have evaluated a wafer map for processing that includes the wafer center and edge area. The CMP dishing measurement can be broken into two distinct regions of measurement: 1) Within-Field dishing and 2) Within-TSV dishing. Greater than 90% correlation with an AFM measurement for all dishing measurement regions has been observed. Less than 0.5% deviation for repeatability data pertaining to this measurement has also been observed.

Metrology of white light interferometer for TSV processing

3D integration technology offers an alternative to traditional packaging designs. In traditional Moore’s law scaling, features are added to the die, with graphics, memory control and logic coprocessors all integrated onto the silicon chip. TSV (through silicon via) processing utilizes vertical electrical interconnects that provide the shortest possible path to establish an electrical connection from the device side to the backside of a die. This indirectly allows continues “Moore”- like scaling while only affecting the device packaging. White light interferometry (WLI) has been used for the measurement of topography, step height and via depth using its short coherence length. The nanometer level resolution of this technique is ideal for TSV measurements in the high aspect ratio vias. In this work, six white light interferometer measurements for TSV processing are discussed along with the importance of these measurements to TSV processing, namely: 1. Post-TSV etch: depth, top CD (TCD) and bottom CD (BCD) 2. Post-TSV liner BCD 3. Post-TSV barrier seed BCD 4. TSV electro-chemically plated (ECP) copper bump step height 5. Post-annealing bump step height 6. TSV CMP dishing These measurement steps have been implemented in-line for advanced technology node TSV process flows at GLOBALFOUNDRIES. The measurements demonstrate 90% correlation to reference metrology and <0.5% repeatability. Cross section SEM was used as a reference for TSV profile and Cu bump measurements while AFM was used as a reference for dishing measurements.