Luke England

Reflow process optimization for micro-bumps applications in 3D technology

In this paper a reflow process for fine-pitch micro-bumps is studied. A mathematical model for the reflow process is proposed and verified by experimental measurements. The influence of reflow profile parameters on the shape of micro-bumps, will be discussed using three commercial reflow ovens. Furthermore, measurement results of bump height variations after reflow over a 300mm wafer will be presented.

Successful void free gap fill of 3µm, high AR via middle, Through Silicon Vias at wafer level

This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, Through Silicon Vias (TSV), of 3μm top entrant critical dimension (CD) and 50μm depth. Higher AR TSV integration is explored due to the lower stress influence of TSVs observed in adjacent CMOS devices.

TSV residual Cu step height analysis by white light interferometry for 3D integration

Cu pumping, or the extrusion of Cu out of a TSV after being subjected to high temperature conditions, is one of the highest risk failure modes to be overcome in the development of TSV-middle integration for 3D packaging technologies. Typical Cu pumping analyses focus on a low number of data points through brute force measurement using cross sectional analysis. The low number of data points gathered for each condition does not provide results with a high statistical confidence level. In addition, it is most likely that the cross section does not provide measurement along the plane that contains the highest amount of Cu pumping, resulting in inaccurate maximum pumping height measurements. In this study, a Cu pumping measurement technique was developed using a production capable scanning white light interferometry (SWLI) system, which enables the collection of hundreds or thousands of individual TSV Cu pumping data points. This enables an accurate statistical comparison between Cu pumping mitigation schemes. Using this technique, multiple TSV plating process and thermal annealing conditions were compared by varying temperature and time to determine the conditions that resulted in the lowest amount of Cu pumping. In addition, an alternate integration scheme was investigated that includes multiple anneal and CMP planarization steps. The experimental results demonstrate that Cu pumping can be kept to a manageable level for high reliability performance.

Process Development and Optimization for 3

This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, through-silicon vias (TSVs), of 3 μm top entrant critical dimension and 50 μm depth. Higher AR TSV integration is explored due to the lower stress and copper pumping influence of TSVs observed in adjacent CMOS devices. The key process improvements demonstrated in this paper include 3 μm TSV etch, dielectric liner coverage, metal barrier and seed layer coverage, and copper electroplating.

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The integration of Through-Silicon Vias (TSVs) in CMOS wafers has the potential to cause performance shifts of devices in close proximity due to mobility change caused by mechanical stress. To ensure successful integration of TSV into a baseline technology, these shifts must be negligible to allow seamless integration of TSVs into circuit designs. As the first publication of its kind by an advanced node foundry, this paper presents results of a study to analyze TSV impact on 14nm FinFET device and analog circuit performance. These include n or p type short and long channel FETs, current mirrors, and operational amplifiers (op-amp). The unique TSV capture pad structure used by GLOBALFOUNDRIES for advanced node TSV integration is discussed. This structure allows for improved TSV middle integration yield and ensures that a good electrical connection from the back-end of line (BEOL) to the TSV is formed. A physical property analysis was also done on the TSV structure to determine capacitance, leakage, and dielectric liner breakdown voltage. Finally, a full suite of characterization measurements were performed on the 14nm FinFET thin wafers to assess the impact of the wafer thinning process on front-end of line (FEOL) devices.

High Aspect Ratio Via-Middle Through-Silicon Vias at Wafer Level

This paper presents the impact of Through Silicon Via (TSV) process on wafer level reliability with respect to front-end of line (FEOL) and back-end of line (BEOL) reliability aspects. A TSV proximity study was performed by placing the TSV at various keep-out zone (KOZ) distances and different orientations of horizontal, vertical, and 45 degrees. FEOL and BEOL test structures were designed using stand-alone devices having TSV at KOZ distance of 2μm, 3μm, 5μm and 7μm and different orientations. Reliability tests show no impact on TSV KOZ on both FEOL and BEOL device performance. Additionally, we also performed a thinning study on the TSV wafers to characterize the impact of the wafer thinning process. We observed negligible difference between pre-thinning and post-thinning measurements and they fall within the expected wafer-to-wafer and lot-to-lot variability of the 14nm baseline process. As part of our ongoing reliability qualification for 14nm TSV reliability tests is currently being performed on these thin wafers.

Impact of TSV integration on 14nm FinFET device performance

Etch is one of the most critical processes for high-aspect ratio TSV as it defines the profile and wafer level depth uniformity of TSV, thus having a great impact on other downstream processes in TSV module and TSV backside reveal. This paper presents the challenges encountered in developing the 6μm × 55μm TSV (6μm diameter × 55μm depth) with a number of continuous process optimizations. These include improvements to the notch below the hard-mask, an increase in the post-etch resist retention, within wafer depth uniformity and higher silicon etch rate improving the throughput. TSV scaling to 3μm × 50μm with a higher aspect ratio is also demonstrated. This paper also describes details for setup of an Automatic Process Controller (APC) for TSV depth control in a manufacturing environment.

Impact of TSV process on 14nm FEOL and BEOL reliability

To date, Plasma Enhanced Chemical Vapor Deposition (PECVD) O3/TEOS has been the prevalent dielectric liner for TSV applications. This process typically results in poor step coverage for high aspect ratio (HAR) TSV scenarios, and also requires a capping layer to provide acceptable reliability performance due to the high moisture content of the O3/TEOS material. This study reports on a high throughput room temperature Atomic Layer Deposition (ALD) batch process for use as a dielectric liner in TSV applications, which provides several advantages over existing processes. Process characterization was completed to achieve a 100nm thickness SiO2 liner for a 6×55μm TSV size with nearly 100% conformal sidewall coverage, demonstrating the usefulness of this process for scaling to 3×50μm TSV size and beyond. Characterization of the ALD SiO2 dielectric liner showed breakdown voltage, leakage, and parasitic capacitance values as good as, or better than, the PECVD O3/TEOS dielectric process of record. In addition, the batch ALD process allows for a significant cost reduction of the overall TSV module. The new ALD SiO2 dielectric liner material was also validated through the downstream TSV fabrication process with no adverse effects.

Process development and optimization for high-aspect ratio through-silicon via (TSV) etch

In this paper the design of a novel IP for 3D IC die-to-die clock synchronization is presented. The proposed design offers notable benefits over the conventional dual DLL based architectures for 3D IC clock synchronization. Simulation results of the IP are presented with GLOBALFOUNDRIES 14nm finFET library, and Through-Silicon Via (TSV) technology.

Room temperature ALD oxide liner for TSV applications

In 3D packages top-die power delivery is a not only limited by back-end of line (technology scaling), but also by the TSV integration scheme, the stacking method and the microbump current-carrying capability. The microbump structure and its electromigration time-to-failure (TTF) rate determine the current carrying capability of each TSV, and this is far lower than the current-carrying capability of a C4 bump. Therefore, the power delivery to the top die(s) needs to be distributed through a network of TSVs that tie into the power grid of the top die. The drawback of such a design is the resistive losses in the BEOL of the bottom-die. In this paper, we highlight these challenges faced by each stacking method, and as a promising solution, we will present the use of a voltage-compensation network with dynamic IR-drop sensors that can be used as part of the power-delivery cell to maintain nominal power delivery during all loading cycles. This can help eliminate the use of off-chip voltage regulator modules.