Sukjae Jang

Wafer-Scale Synthesis and Transfer of Graphene Films

We developed means to produce wafer scale, high-quality graphene films as large as 3 in. wafer size on Ni and Cu films under ambient pressure and transfer them onto arbitrary substrates through instantaneous etching of metal layers. We also demonstrated the applications of the large-area graphene films for the batch fabrication of field-effect transistor (FET) arrays and stretchable strain gauges showing extraordinary performances. Transistors showed the hole and electron mobilities of the device of 1100 +/- 70 and 550 +/- 50 cm(2)/(V s) at drain bias of -0.75 V, respectively. The piezo-resistance gauge factor of strain sensor was approximately 6.1. These methods represent a significant step toward the realization of graphene devices in wafer scale as well as application in optoelectronics, flexible and stretchable electronics.

All Graphene-Based Thin Film Transistors on Flexible Plastic Substrates

High-performance, flexible all graphene-based thin film transistor (TFT) was fabricated on plastic substrates using a graphene active layer, graphene oxide (GO) dielectrics, and graphene electrodes. The GO dielectrics exhibit a dielectric constant (3.1 at 77 K), low leakage current (17 mA/cm(2)), breakdown bias (1.5 × 10(6) V/cm), and good mechanical flexibility. Graphene-based TFTs showed a hole and electron mobility of 300 and 250 cm(2)/(V·s), respectively, at a drain bias of -0.1 V. Moreover, graphene TFTs on the plastic substrates exhibited remarkably good mechanical flexibility and optical transmittance. This method explores a significant step for the application of graphene toward flexible and stretchable electronics.

Flexible, transparent single-walled carbon nanotube transistors with graphene electrodes.

This paper reports a mechanically flexible, transparent thin film transistor that uses graphene as a conducting electrode and single-walled carbon nanotubes (SWNTs) as a semiconducting channel. These SWNTs and graphene films were printed on flexible plastic substrates using a printing method. The resulting devices exhibited a mobility of ∼ 2 cm(2) V(-1) s -1), On/Off ratio of ∼ 10(2), transmittance of ∼ 81% and excellent mechanical bendability.

Multifunctional Graphene Optoelectronic Devices Capable of Detecting and Storing Photonic Signals

The advantages of graphene photodetectors were utilized to design a new multifunctional graphene optoelectronic device. Organic semiconductors, gold nanoparticles (AuNPs), and graphene were combined to fabricate a photodetecting device with a nonvolatile memory function for storing photonic signals. A pentacene organic semiconductor acted as a light absorption layer in the device and provided a high hole photocurrent to the graphene channel. The AuNPs, positioned between the tunneling and blocking dielectric layers, acted as both a charge trap layer and a plasmonic light scatterer, which enable storing of the information about the incident light. The proposed pentacene-graphene-AuNP hybrid photodetector not only performed well as a photodetector in the visible light range, it also was able to store the photonic signal in the form of persistent current. The good photodetection performance resulted from the plasmonics-enabled enhancement of the optical absorption and from the photogating mechanisms in the pentacene. The device provided a photoresponse that depended on the wavelength of incident light; therefore, the signal information (both the wavelength and intensity) of the incident light was effectively committed to memory. The simple process of applying a negative pulse gate voltage could then erase the programmed information. The proposed photodetector with the capacity to store a photonic signal in memory represents a significant step toward the use of graphene in optoelectronic devices.

Graphene–Graphene Oxide Floating Gate Transistor Memory

A novel transparent, flexible, graphene channel floating-gate transistor memory (FGTM) device is fabricated using a graphene oxide (GO) charge trapping layer on a plastic substrate. The GO layer, which bears ammonium groups (NH3+), is prepared at the interface between the crosslinked PVP (cPVP) tunneling dielectric and the Al2 O3 blocking dielectric layers. Important design rules are proposed for a high-performance graphene memory device: (i) precise doping of the graphene channel, and (ii) chemical functionalization of the GO charge trapping layer. How to control memory characteristics by graphene doping is systematically explained, and the optimal conditions for the best performance of the memory devices are found. Note that precise control over the doping of the graphene channel maximizes the conductance difference at a zero gate voltage, which reduces the device power consumption. The proposed optimization via graphene doping can be applied to any graphene channel transistor-type memory device. Additionally, the positively charged GO (GO-NH3+) interacts electrostatically with hydroxyl groups of both UV-treated Al2 O3 and PVP layers, which enhances the interfacial adhesion, and thus the mechanical stability of the device during bending. The resulting graphene-graphene oxide FGTMs exhibit excellent memory characteristics, including a large memory window (11.7 V), fast switching speed (1 μs), cyclic endurance (200 cycles), stable retention (10(5) s), and good mechanical stability (1000 cycles).

One step synthesis of Au nanoparticle-cyclized polyacrylonitrile composite films and their use in organic nano-floating gate memory applications

In this study, we synthesized Au nanoparticles (AuNPs) in polyacrylonitrile (PAN) thin films using a simple annealing process in the solid phase. The synthetic conditions were systematically controlled and optimized by varying the concentration of the Au salt solution and the annealing temperature. X-ray photoelectron spectroscopy (XPS) confirmed their chemical state, and transmission electron microscopy (TEM) verified the successful synthesis, size, and density of AuNPs. Au nanoparticles were generated from the thermal decomposition of the Au salt and stabilized during the cyclization of the PAN matrix. For actual device applications, previous synthetic techniques have required the synthesis of AuNPs in a liquid phase and an additional process to form the thin film layer, such as spin-coating, dip-coating, Langmuir–Blodgett, or high vacuum deposition. In contrast, our one-step synthesis could produce gold nanoparticles from the Au salt contained in a solid matrix with an easy heat treatment. The PAN:AuNPs composite was used as the charge trap layer of an organic nano-floating gate memory (ONFGM). The memory devices exhibited a high on/off ratio (over 106), large hysteresis windows (76.7 V), and a stable endurance performance (>3000 cycles), indicating that our stabilized PAN:AuNPs composite film is a potential charge trap medium for next generation organic nano-floating gate memory transistors.

Flexible thin flim transistor using printed single-walled carbon nanotubes

Flexible thin film transistors (TFT) were fabricated with randomly oriented single-walled carbon nanotubes (SWNTs) synthesized selectively on a designed array of catalyst photoresists using the plasma-enhanced chemical vapor deposition (PECVD) method. The process involves SWNTs growth on SiO2/Si substrates, followed by transfer-printing of tubes onto thin, flexible sheets of plastic. Electrical measurements on the resulting devices reveal good characteristics. These results might be of interest for various applications of SWNTs in flexible electronics.

Controllable Switching Filaments Prepared via Tunable and Well-Defined Single Truncated Conical Nanopore Structures for Fast and Scalable SiOx Memory

The controllability of switching conductive filaments is one of the central issues in the development of reliable metal-oxide resistive memory because the random dynamic nature and formation of the filaments pose an obstacle to desirable switching performance. Here, we introduce a simple and novel approach to control and form a single silicon nanocrystal (Si-NC) filament for use in SiOx memory devices. The filament is formed with a confined vertical nanoscale gap by using a well-defined single vertical truncated conical nanopore (StcNP) structure. The physical dimensions of the Si-NC filaments such as number, size, and length, which have a significant influence on the switching properties, can be simply engineered by the breakdown of an Au wire through different StcNP structures. In particular, we demonstrate that the designed SiOx memory junction with a StcNP of pore depth of ∼75 nm and a bottom diameter of ∼10 nm exhibited a switching speed of up to 6 ns for both set and reset process, significantly faster than reported SiOx memory devices. The device also exhibited a high ON-OFF ratio, multistate storage ability, acceptable endurance, and retention stability. The influence of the physical dimensions of the StcNP on the switching features is discussed based on the simulated temperature profiles of the Au wire and the nanogap size generated inside the StcNP structure during electromigration.