Christian Holfeld

EUV lithography at the 22nm technology node

We are evaluating the readiness of extreme ultraviolet (EUV) lithography for insertion into production at the 15 nm technology node by integrating it into standard semiconductor process flows because we believe that device integration exercises provide the truest test of technology readiness and, at the same time, highlight the remaining critical issues. In this paper, we describe the use of EUV lithography with the 0.25 NA Alpha Demo Tool (ADT) to pattern the contact and first interconnect levels of a large (~24 mm x 32 mm) 22 nm node test chip using EUV masks with state-of-the-art defectivity (~0.3 defects/cm2). We have found that: 1) the quality of EUVL printing at the 22 nm node is considerably higher than the printing produced with 193 nm immersion lithography; 2) printing at the 22 nm node with EUV lithography results in higher yield than double exposure double-etch 193i lithography; and 3) EUV lithography with the 0.25 NA ADT is capable of supporting some early device development work at the 15 nm technology node.

Actinic imaging of native and programmed defects on a full-field mask

We describe the imaging and characterization of native defects on a full field extreme ultraviolet (EUV) mask, using several reticle and wafer inspection modes. Mask defect images recorded with the SEMATECH Berkeley Actinic Inspection Tool (AIT), an EUV-wavelength (13.4 nm) actinic microscope, are compared with mask and printed-wafer images collected with scanning electron microscopy (SEM) and deep ultraviolet (DUV) inspection tools. We observed that defects that appear to be opaque in the SEM can be highly transparent to EUV light, and inversely, defects that are mostly transparent to the SEM can be highly opaque to EUV. The nature and composition of these defects, whether they appear on the top surface, within the multilayer coating, or on the substrate as buried bumps or pits, influences both their significance when printed, and their detectability with the available techniques. Actinic inspection quantitatively predicts the characteristics of printed defect images in ways that may not be possible with non-EUV techniques.

An Investigation of EUV Lithography Defectivity

We have used ASMLs full field step-and-scan exposure tool for extreme ultraviolet lithography (EUVL), known as an Alpha Demo Tool, to investigate one of the critical issues identified for EUVL, defectivity associated with EUV masks. The main objective for this work was to investigate the infrastructure currently in place to examine defects on a EUV reticle and identify their consequence in exposed resist. Unlike many previous investigations this work looks at naturally occurring defects in a EUV exposed metal layer from a 45 nm node device. The EUV exposure was also integrated into a standard process flow where the other layers were patterned using more conventional 193-nm lithography techniques. This presentation correlates reticle level defectivity to resulting wafer exposures. Defect inspection data from both the 28xx family of KLA-Tencor wafer inspection tool and Terascan reticle inspection tools are presented. Defect populations were characterized with a KLA 5200 Review SEM. Observed defectivity modes were analyzed using both conventional defect inspection methodology as well as advanced techniques in order to gain further insight. We find good correlations between reticle level defects and the resulting wafer exposure defects.

Wafer inspection as alternative approach to mask defect qualification

Defect inspection is one of the major challenges in the manufacturing process of photomasks. The absence of any printing defect on patterned mask is an ultimate requirement for the mask shop, and an increasing effort is spent in order to detect and subsequently eliminate these defects. Current DUV inspection tools use wavelengths five times or more larger than the critical defect size on advanced photomasks. This makes the inspectability of high-end mask patterns (including strong OPC and small SRAFs) and sufficient defect sensitivity a real challenge. The paper evaluates the feasibility of inspecting the printed wafer as an alternative way for the high-sensitivity defect inspection of photomasks. Defects originating in the mask can efficiently be filtered as repeated defects in the various dies on wafer. Using a programmed-defect mask of 65-nm technology, a reliable detection of the printing defects was achieved with an optimized inspection process. These defects could successfully be traced back to the photomask in a semi-automated process in order to enable a following repair step. This study shows that wafer inspection is able to provide a full defect qualification of advanced photomasks with the specific advantage of assessing the actual printability of arbitrary defects.

Demonstration of phase-shift masks for extreme-ultraviolet lithography

We report on a method to produce any type of phase-shift masks for EUV lithography. We have successfully fabricated an unattenuated phase-shift mask consisting of phase patterns and confirmed the expected performance of such a mask through resist printing at λ=13.3 nm. Finally actinic metrology reveals that these etched-multilayer masks, left without a capping layer, tend to degrade over time.

EUV mask image placement management in writing, registration, and exposure tools

Due to the non-telecentricity of the EUV illumination, the EUV mask flatness budget dictates the use of an electrostatic chuck in the exposure tool. Since the mask backside flattening provided by the electrostatic chuck in the exposure tool is very different from the 3-point mounts currently employed to hold reticles in pattern generation and registration measurement tools, this raises the question of which mounting techniques to apply in future patterning and registration tools. In case drastic changes need to be made to the tool configurations, it is important to know, and as early as possible, whether backside chucking of reticles, via an electrostatic or vacuum chuck, is absolutely required or if a 3-point mounting scheme can suffice in these tools. Using finite element simulations, the effects on EUV mask image placement of stressed layers and their patterning, as well as substrate and chuck non-flatness were predicted for these different conditions. The results can be used to calculate image placement error budgets and determine what substrate and blank specifications are needed for the implementation of EUV at the 32-nm node.

Assessing EUV mask defectivity

This paper assesses the readiness of EUV masks for pilot line production. The printability of well characterized reticle defects, with particular emphasis on those reticle defects that cause electrical errors on wafer test chips, is investigated. The reticles are equipped with test marks that are inspected in a die-to-die mode (using DUV inspection tool) and reviewed (using a SEM tool), and which also comprise electrically testable patterns. The reticles have three modules comprising features with 32 nm ground rules in 104 nm pitch, 22 nm ground rules with 80 nm pitch, and 16 nm ground rules with 56 nm pitch (on the wafer scale). In order to determine whether specific defects originate from the substrate, the multilayer film, the absorber stack, or from the patterning process, the reticles were inspected after each fabrication step. Following fabrication, the reticles were used to print wafers on a 0.25 NA full-field ASML EUV exposure tool. The printed wafers were inspected with state of the art bright-field and Deep UV inspection tools. It is observed that the printability of EUV mask defects down to a pitch of 56 nm shows a trend of increased printability as the pitch of the printed pattern gets smaller - a well established trend at larger pitches of 80 nm and 104 nm, respectively. The sensitivity of state-of-the-art reticle inspection tools is greatly improved over that of the previous generation of tools. There appears to be no apparent decline in the sensitivity of these state-of-the-art reticle inspection tools for higher density (smaller) patterns on the mask, even down to 56nm pitch (1x). Preliminary results indicate that a blank defect density of the order of 0.25 defects/cm2 can support very early learning on EUV pilot line production at the 16nm node.

EUVL mask manufacturing: technologies and results

Extreme Ultraviolet Lithography (EUVL) is the favourite next generation lithography candidate for IC device manufacturing with feature sizes beyond 32nm. Different stacks and manufacturing concepts have been published for the fabrication of the reflective EUVL masks. Patterning processes for two different absorber-buffer combinations on top of the reflective multi layer mirror have been developed. A TaN/SiO2 absorber-buffer stack was provided by supplier A and TaBN/Cr by supplier B. In addition both absorbers were covered by an anti reflective coating (ARC) layer. An e-beam patterned 300nm thick film of Fuji FEP171 was used as resist mask. We optimized the etching processes for maximum selectivities between absorber, buffer and capping layers on the one hand and rectangular profiles and low etch bias on the other hand. While both TaN based absorbers have been dry etched in an UNAXIS mask etcher III, wet and dry etch steps have been evaluated for the two different buffer layers. The minimum feature size of lines and holes in our test designs was 100nm. After freezing the processes a proximity correction was determined considering both, the influence of electron scattering due to e-beam exposure and the influence of the patterning steps. Due to the correction an outstanding linearity and iso/dense bias on different test designs was achieved. Various masks for printing experiments at the small-field Micro Exposure Tool (MET) in Berkeley and the fabrication of the ASML α-tool setup mask within the European MEDEA+ EXTUMASK project were done using the developed processes. Finally, we will compare and discuss the results of the two stack approaches.

Comparison of EUV mask architectures by process window analysis

Several masks have been fabricated and exposed with the small-field Micro Exposure Tool (MET) at the Advanced Light Source (ALS) synchrotron in Berkeley using EUV radiation at 13.5 nm wavelength. Investigated mask types include two different absorber masks with TaN absorber as well as an etched multilayer mask. The resulting printing performance under different illumination conditions were studied by process window analysis on wafer level. Features with resolution of 60 nm and below were resolved with all masks. The TaN absorber masks with different stack thicknesses showed a similar size of process window. The differences in process windows for line patterns were analyzed for 60 nm patterns. The implications on the choice of optimum mask architecture are discussed.

Lithographic performance evaluation of a contaminated extreme ultraviolet mask after cleaning

The effect of surface contamination and subsequent mask surface cleaning on the lithographic performance of an extreme ultraviolet (EUV) mask is investigated. SEMATECH’s Berkeley microfield exposure tool printed 40 and 50 nm line and space (L/S) patterns are evaluated to compare the performance of a contaminated and cleaned mask to an uncontaminated mask. Since the two EUV masks have different absorber architectures, optical imaging models and aerial image calculations were performed to determine any expected differences in performance. The measured and calculated Bossung curves, process windows, and exposure latitudes for the two sets of L/S patterns are compared to determine how the contamination and cleaning impacts the lithographic performance of EUV masks. The observed differences between the two masks are shown to be well within the expected process variation of 10%, indicating that the cleaning process did not appreciably affect the mask performance.