Sumit Dutta

The Third US Naval Observatory CCD Astrograph Catalog (UCAC3)

The second US Naval Observatory (USNO) CCD Astrograph Catalog, UCAC2 was released in 2003 July. Positions and proper motions for 48,330,571 sources (mostly stars) are available on 3 CDs, supplemented with Two Micron All Sky Survey photometry for 99.5% of the sources. The catalog covers the sky area from -90° to +40° declination, going up to +52° in some areas; this completely supersedes the UCAC1 released in 2001. Current epoch positions are obtained from observations with the USNO 8 inch (0.2 m) Twin Astrograph equipped with a 4K CCD camera. The precision of the positions are 15–70 mas, depending on magnitude, with estimated systematic errors of 10 mas or below. Proper motions are derived by using over 140 ground- and space-based catalogs, including Hipparcos/Tycho and the AC2000.2, as well as yet unpublished remeasures of the AGK2 plates and scans from the NPM and SPM plates. Proper-motion errors are about 1–3 mas yr-1 for stars to 12th magnitude, and about 4–7 mas yr-1 for fainter stars to 16th magnitude. The observational data, astrometric reductions, results, and important information for the users of this catalog are presented.

Reduction of hysteresis for carbon nanotube mobility measurements using pulsed characterization

We describe a pulsed measurement technique for suppressing hysteresis for carbon nanotube (CNT) device measurements in air, vacuum, and over a wide temperature range (80-453 K). Varying the gate pulse width and duty cycle probes the relaxation times associated with charge trapping near the CNT, found to be up to the 0.1-10 s range. Longer off times between voltage pulses enable consistent, hysteresis-free measurements of CNT mobility. A tunneling front model for charge trapping and relaxation is also described, suggesting trap depths up to 4-8 nm for CNTs on SiO2. Pulsed measurements will also be applicable for other nanoscale devices such as graphene, nanowires, or molecular electronics, and could enable probing trap relaxation times in a variety of material system interfaces.

Thermal dissipation and variability in electrical breakdown of carbon nanotube devices

We study high-field electrical breakdown and heat dissipation from carbon nanotube CNT devices on SiO2 substrates. The thermal “footprint” of a CNT caused by van der Waals interactions with the substrate is revealed through molecular dynamics simulations. Experiments and modeling find the CNT-substrate thermal coupling scales proportionally with CNT diameter and inversely with SiO2 surface roughness d /. Comparison of diffuse mismatch modeling and data reveals the upper limit of thermal coupling 0.4 W K x7f1 m x7f1 per unit CNT length at room temperature, 130 MW K x7f1 m x7f2 per unit area, and 0.7 W K x7f1 m x7f1 at 600 °C for the largest diameter 3.2 nm CNTs. We also find semiconducting CNTs can break down prematurely and display more variability due to dynamic shifts in threshold voltage, which metallic CNTs are immune to; this poses a fundamental challenge for selective electrical breakdowns in CNT electronics.

Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls

Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation.

A Web Service and Interface for Remote Electronic Device Characterization

A lightweight Web Service and a Web site interface have been developed, which enable remote measurements of electronic devices as a “virtual laboratory” for undergraduate engineering classes. Using standard browsers without additional plugins (such as Internet Explorer, Firefox, or even Safari on an iPhone), remote users can control a Keithley source-measurement unit and monitor results in real time from anywhere on the Internet. As an in-class example, students in a solid-state electronics course used the Web site interface to make real-time transistor measurements. Recommendations are made on how to best integrate the interface into electronics classes based on the student assignment responses. The present interface is flexible and could be expanded to many other devices and instruments. The source code has been openly posted online.

Avalanche, joule breakdown and hysteresis in carbon nanotube transistors

We explore several aspects of reliability in carbon nanotube transistors, including their physical dependence on diameter. Avalanche behavior is found at high fields (5–10 V/μm), while Joule breakdown is reached at high current and heating, in the presence of oxygen. Finally, we describe a method for minimizing hysteresis effects via pulsed measurements.

Micromagnetic modeling of domain wall motion in sub-100-nm-wide wires with individual and periodic edge defects

Reducing the switching energy of devices that rely on magnetic domain wall motion requires scaling the devices to widths well below 100 nm, where the nanowire line edge roughness (LER) is an inherent source of domain wall pinning. We investigate the effects of periodic and isolated rectangular notches, triangular notches, changes in anisotropy, and roughness measured from images of fabricated wires, in sub-100-nm-wide nanowires with in-plane and perpendicular magnetic anisotropy using micromagnetic modeling. Pinning fields calculated for a model based on discretized images of physical wires are compared to experimental measurements. When the width of the domain wall is smaller than the notch period, the domain wall velocity is modulated as the domain wall propagates along the wire. We find that in sub-30-nm-wide wires, edge defects determine the operating threshold and domain wall dynamics.

The Spatial Resolution Limit for an Individual Domain Wall in Magnetic Nanowires

Magnetic nanowires are the foundation of several promising nonvolatile computing devices, most notably magnetic racetrack memory and domain wall logic. Here, we determine the analog information capacity in these technologies, analyzing a magnetic nanowire containing a single domain wall. Although wires can be deliberately patterned with notches to define discrete positions for domain walls, the line edge roughness of the wire can also trap domain walls at dimensions below the resolution of the fabrication process, determining the fundamental resolution limit for the placement of a domain wall. Using a fractal model for the edge roughness, we show theoretically and experimentally that the analog information capacity for wires is limited by the self-affine statistics of the wire edge roughness, a relevant result for domain wall devices scaled to regimes where edge roughness dominates the energy landscape in which the walls move.

Floating-point unit design with nano-electro-mechanical (NEM) relays

Digital circuits made with nano-electro-mechanical (NEM) relays offer energy-efficiency benefits over CMOS since they have zero leakage power and can offer circuit level performance that competes with CMOS. In this paper we show how new relay circuit design techniques combined with those we already demonstrated on smaller relay blocks enable us to optimize the design of the most complex arithmetic unit, the floating-point unit (FPU). The energy, performance, and area trade-offs of FPU designs with NEM relays are examined and compared with those of state-of-the-art CMOS designs in an equivalent scaled process. Circuits that are critical path bottlenecks for the FPU specifically, most notably the leading zero detector (LZD) and leading zero anticipator (LZA), are optimized with new relay-tailored circuit techniques. These optimizations reduce the NEM relay FPU latency from 71 mechanical delays in an optimal-CMOS-style implementation to 16 mechanical delays in a generalized custom NEM relay implementation. In a 90 nm process node, the FPU designed with NEM relays is projected to achieve 15× lower energy per operation compared to the FPU designed with CMOS.

Effect of Magnetostatic Interactions on Stochastic Domain Wall Motion in Sub-100 nm Wide Nanowires

Magnetic field-driven domain wall motion is investigated in closely spaced sub-100 nm wide Co nanowires. Anticorrelations appear in the spatial distribution of pinning sites within weakly interacting nanowires, with a reduced probability of pinning adjacent to another pinning site over a mean correlation length similar to the line width roughness. In contrast, strong magnetostatic interactions between domain walls in adjacent nanowires eliminate the correlations, reducing the domain wall propagation distance for a given applied magnetic field.