Sun-Phil Nah

Automatic Modulation Recognition of Digital Signals using Wavelet Features and SVM

This paper presents modulation classification method capable of classifying incident digital signals without a priori information using WT key features and SVM. These key features for modulation classification should have good properties of sensitive with modulation types and insensitive with SNR variation. In this paper, the 4 key features using WT coefficients, which have the property of insensitive to the changing of noise, are selected. The numerical simulations using these features are performed. We investigate the performance of the SVM-DDAG classifier for classifying 8 digitally modulated signals using only 4 WT key features (i.e., 4 level scale), and compare with that of decision tree classifier to adapt the modulation classification module in software radio. Results indicated an overall success rate of 95% at the SNR of 10dB in SVM-DDAG classifier on an AWGN channel.

Automatic Modulation Recognition using Support Vector Machine in Software Radio Applications

Most of the algorithms proposed in the literature deal with the problem of digital modulation classification. This paper discusses the modulation classifiers capable of classifying both analog and digital modulation signals in military and civilian communications applications. A total of 7 statistical signal features are extracted and used to classify 9 modulation signals. In this paper, we investigate the performance of the two types of SVM classifiers and compare the performance of these SVM classifiers with that of decision tree based and minimum distance based classifiers. In numerical simulations, SVM classifiers indicate good performance (i.e. probability of correct classification > 95%) on an AWGN channel, even at signal-to-noise ratios as low as 5 dB.

An 8-b 1GS/s Fractional Folding CMOS Analog-to- Digital Converter with an Arithmetic Digital Encoding Technique

A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is 2.1 mm 2 (ADC core : 1.4 mm 2 , calibration engine : 0.7

Automatic Classification of Digitally Modulated Signals Based on K-Nearest Neighbor

In this paper, we propose an automatic classification method for eight digitally modulated signals, such as 2FSK, 4FSK, MSK, BPSK, QPSK, 8PSK, 16QAM, and 64QAM. The method uses spectral correlation density and high-order cumulants as features. For feature classification, K-nearest neighbor algorithm is used. Simulation results are demonstrated to evaluate the proposed scheme.

A 12b 100 MS/s Three-Step Hybrid Pipeline ADC Based on Time-Interleaved SAR ADCs

This work proposes a 12b 100 MS/s 0.11 m CMOS three-step hybrid pipeline ADC for high- speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual- channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a 0.11 m CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of 1.34 mm 2 and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.

Digitally Modulated Signal Classification based on Higher Order Statistics of Cyclostationary Process

In this paper, we propose an automatic modulation classification method for ten digitally modulated baseband signals, such as 2-FSK, 4-FSK, 8-FSK, MSK, BPSK, QPSK, 8-PSK, 16-QAM, 32-QAM, and 64-QAM based on higher order statistics of cyclostationary process. The first order cyclic moments and higher order cyclic cumulants of the signal are used as features of the modulation signals. The proposed method consists of two stages. At the first stage, we classify modulation signals as M-FSK and non-FSK using peaks of the first order cyclic moment. At the next step, we apply the Gaussian mixture model-based classifier to classify non-FSK. Simulation results are demonstrated to evaluate the proposed scheme. The results show high probability of classification even in the presence of frequency and phase offsets.

An 8-b cascaded folding A/D converter with a new fully differential source follower

Conventionally, source followers have been used at the block of track-and-hold amplifiers (THA) for highspeed medium-bit analog-to-digital converters (ADCs). Even though the input signals of an ADC are fully differential, two single-ended source followers should be normally used. This is because differential source followers have some drawbacks. In this study, a wideband fully differential source follower is presented to obtain maximum efficiency of a fully differential THA. Because a cross coupling technique at the differential nodes is adopted, the performance of the proposed source follower is superior to the performance of conventional followers. The result of Spurious Free Dynamic Range(SFDR) is -66.92dBc for Fin=Fs/2 at FS=500MHz. The SFDR of the proposed source follower is better by about 8.6dB than the SFDR of a conventional source follower under the same experimental conditions. To verify them, an 8-b cascaded folding ADC which includes the proposed source follower is fabricated with a 0.13um CMOS technology.

Indoor sensor array test-bed(SATB) for direction finding applications at communication-band

An efficient sensor array test-bed compatible with direction finding indoor test applications at communication-band is developed. It provides the test flexibility of DF accuracy including the different antenna configuration, DF algorithms and modulation schemes considering with instrumental errors induced by multi-channel receivers. The ability of test-bed is useful for system designers who are involved in the development of DF system at communication-band. Further research will be investigated the DF accuracy of FHSS and the effects of interference signal, frequency offset and integration time.

A Multi-Channel Correlative Vector Direction Finding System Using Active Dipole Antenna Array for Mobile Direction Finding Applications

A fast correlative vector direction finding(CVDF) system using active dipole antenna array for mobile direction finding(DF) applications is presented. To develop the CVDF system, the main elements such as active dipole antenna, multi-channel direction finder, and search receiver are designed and analyzed. The active antenna is designed as composite structure to improve the filed strength sensitivity over the wide frequency range, and the multi-channel direction finder and search receiver are designed using DDS-based PLL with settling time of below 35 us to achieve short signal processing time. This system provides the capabilities of the high DF sensitivity over the wide frequency range and allows for high probability of intercept and accurate angle of arrival(AOA) estimation for agile signals. The design and performance analysis according to the external noise and modulation schemes of the CVDF system with five-element circular array are presented in detail.

Design of a 45nm 8-bit 2GS/s 250mW CMOS folding A/D converter with an adaptive digital error correction technique

An 8-bit 2GS/s 250mW low power folding A/D converter(ADC) with a 45nm CMOS technology is described. In order to reduce the power consumption, a new folding block with a shut-down circuit is proposed. The role of shut-down circuit selectively cuts off the power supply of folding amplifiers, according to the input analog voltage. Further, an adaptive digital error correction technique is discussed to reduce the code errors. The proposed ADC has been fabricated with a 1.2V 45nm 1-poly 8-metal CMOS process. The effective chip area is 1.98mm2 (ADC core : 1.1mm2, Calibration : 0.88mm2) and the power consumption is about 250mW. The measured SNDR is 46dB at the conversion rate of 2GS/s. The measured values of INL and DNL are within 2.5LSB and 1.0 LSB, respectively.