Minkyu Song

Design of a high performance 32/spl times/32-bit multiplier with a novel sign select Booth encoder

In this paper, a high performance 32/spl times/32-bit multiplier for a DSP core is proposed. The multiplier is composed of a novel sign select Booth encoder, an efficient data compressor block with a novel compound full-adder, and a 64-bit conditional sum adder with a separated carry generation block. The proposed 32/spl times/32-bit multiplier is designed by a full-custom method and there are about 28000 transistors in an active area of 1.59 mm/spl times/1.68 mm with 0.6 /spl mu/m CMOS technology. From the experimental results, the multiplication time of the 32/spl times/32-bit multiplier is about 9.8 ns at a 3.3 V power supply, and it consumes about 186 mW at 100 MHz.

An 8-bit 200 MSPS CMOS A/D converter for analog interface module of TFT-LCD driver

A 3 V 8-bit 200 MSPS CMOS folding/interpolation A/D converter for analog interface module of TFT-LCD Driver is proposed. It is composed of both a coarse ADC and a fine ADC whose FR (Folding Rate) is 8, NFB (Number of Folding Block) is 4, and IR (interpolation Rate) is 8, respectively. For the purpose of improving SNDR, distributed track-and-hold circuits are included at the input stage. In order to obtain a high speed operation and low power consumption, further, a novel analog latch and digital encoder based on a fast compression algorithm are proposed. The chip has been fabricated with a 0.35 /spl mu/m 2-poly 3-metal CMOS technology. The effective chip area is about 1.2 mm/spl times/0.8 mm and it dissipates about 210 mW at 3 V power supply. The INL and DNL are within 1 LSB, respectively. The SNDR is about 43 dB, when the input frequency reaches 10 MHz at 200 MHz clock frequency.

An Enhanced Dynamic-Range CMOS Image Sensor Using a Digital Logarithmic Single-Slope ADC

Many kinds of wide-dynamic-range (DR) CMOS image sensors (CIS) have been developed, such as a multiple sampling, a multiple exposure technique, etc. However, those techniques have some drawbacks of noise increasing, large power consumption, and huge chip area. In this brief, a new digital logarithmic single-slope analog-to-digital converter (SS-ADC) with a digital counter is described. Since the proposed scheme is easily implemented with a simple algorithm, we can reduce power consumption and chip area drastically. Further, the logarithmic SS-ADC enhances the DR by 24 dB. The proposed ADC, which has been fabricated using a 0.13- μm CIS process, achieves a signal-to-noise-plus-distortion ratio of 57.6 dB at 50 kS/s.

Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA (320 x 240) resolution. The fabricated chip size is 5 mm x 3 mm, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

A two-step A/D conversion and column self-calibration technique for low noise CMOS image sensors.

In this paper, a 120 frames per second (fps) low noise CMOS Image Sensor (CIS) based on a Two-Step Single Slope ADC (TS SS ADC) and column self-calibration technique is proposed. The TS SS ADC is suitable for high speed video systems because its conversion speed is much faster (by more than 10 times) than that of the Single Slope ADC (SS ADC). However, there exist some mismatching errors between the coarse block and the fine block due to the 2-step operation of the TS SS ADC. In general, this makes it difficult to implement the TS SS ADC beyond a 10-bit resolution. In order to improve such errors, a new 4-input comparator is discussed and a high resolution TS SS ADC is proposed. Further, a feedback circuit that enables column self-calibration to reduce the Fixed Pattern Noise (FPN) is also described. The proposed chip has been fabricated with 0.13 μm Samsung CIS technology and the chip satisfies the VGA resolution. The pixel is based on the 4-TR Active Pixel Sensor (APS). The high frame rate of 120 fps is achieved at the VGA resolution. The measured FPN is 0.38 LSB, and measured dynamic range is about 64.6 dB.

Design of a 1.8 V 6-bit Folding Interpolation CMOS A/D Converter with a 0.93 [pJ/convstep] Figure-of-Merit

In this paper, a CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type with a resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones, an averaging folder technique, and a compensated resistive interpolation technique are proposed. Further, an autoswitching encoder for efficient digital processing is also presented. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93 [pJ/convstep]. The active chip occupies an area of 0.28mm2 in 0.18μm CMOS technology.

A CMOS Current-Steering D/A Converter With Full-Swing Output Voltage and a Quaternary Driver

This brief describes a CMOS current-steering digital-to-analog converter (D/A converter, DAC) with a full-swing output signal. Generally, a normal current-steering DAC cannot have a full-swing output signal because conventional DACs have an inevitable voltage drop at the output current cell. In order to improve the drawbacks, we propose a new scheme of quaternary driver and an output current cell composed of both nMOS and pMOS. First, the nMOS operates from the power supply to the half of the power supply. Second, the pMOS operates independently from the half of the power supply to the ground voltage. Then, the final output voltage is obtained through a multiplexer that is driven by a quaternary driver that selects the optimized current cell. A 6-bit 1-GS/s current-steering DAC has been fabricated with Dongbu 0.11-μm 1-poly 6-metal (1P6M) CMOS technology to verify the performance of the proposed full-swing DAC. The effective chip area is 0.46 mm2, and power consumption is about 19.1 mW. The measured results reveal that the DAC has a full-swing output signal.

A low noise CMOS image sensor with a 14-bit two-step single-slope ADC and a column self-calibration technique

In this paper, a low-noise CMOS Image Sensor (CIS) based on a 14-bit Two-Step Single-Slope ADC (TS SS ADC) and a column self-calibration technique is proposed. The TS SS ADC is good for the video system which requires fast operation because its conversion speed is faster than the Single Slope ADC (SS ADC) by more than 10 times. However, there are a lot of errors in the circuit operation on the connection point between the coarse block and the fine block due to the 2-step composition of the TS SS ADC. This makes it difficult to implement the TS SS ADC into the high resolution more than 10-bit and the product. In order to improve the drawbacks of TS SS ADC, a new 4-input comparator is discussed. Further, a column self-calibration technique to reduce the Fixed Pattern Noise (FPN) is also described. The chip has been fabricated by Samsung 0.13μm CIS technology. The measured conversion time of the ADC is 17μs and the high frame rate of 120 frames/s (fps) is achieved at the VGA resolution. The measured column FPN is 0.38LSB, and it is much lower than the other reported ones.

Design of a 6-bit 1GSPS fully folded CMOS A/D converter for Ultra Wide Band (UWB) applications

In this paper, a CMOS analog-to-digital converter (ADC) for Ultra Wide Band (UWB) applications with a 6-bit 1GSPS at 1.8 V is described. The architecture of the proposed ADC is based on a fully folded ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) is proposed. Further, a novel layout technique is introduced for compact area. With the clock speed of 1 GHz, the ADC achieves an effective resolution bandwidth (ERBW) of 200 MHz, while consuming only 60 mW of power. The measured INL and DNL are within plusmn0.7LSB, plusmn0.5LSB, respectively. The measured SNDR is 33.64 dB, when Fin=100 MHz at Fs=1 GHz. The active chip occupies an area of 0.27 mm2 in 0.18 mum CMOS technology.

Design of a 1.8V 8-bit 500MSPS folding-interpolation CMOS A/D converter with a folder averaging technique

In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 500 MSPS at 1.8 V is designed. The architecture of the proposed ADC is based on a Folding ADC with a cascaded-folding and a cascaded-interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18mu m 1-poly 5-metal CMOS technology. The active chip area is 0.79 mm2 and it consumes about 200 mW at 1.8 V power supply. The DNL and INL are within plusmn0.6/plusmn0.6LSB, respectively. The measured result of SNDR is 47.05dB.