Gyu-Hong Kim

A 14 nm FinFET 128 Mb SRAM With V

Two 128 Mb dual-power-supply SRAM chips are fabricated in a 14 nm FinFET technology. A 0.064 μm2 and a 0.080 μm2 6T SRAM bitcells are designed for high-density (HD) and high-performance (HP) applications. To improve VMIN of the high-density SRAM, a negative bitline scheme (NBL) is adopted as a write-assist technique. Then, the disturbance-noise reduction (DNR) scheme is proposed as a read-assist circuit to improve the VMIN of the high-performance SRAM. The 128 Mb 6T-HD SRAM test-chip is fully demonstrated featuring 0.50 VMIN with 200 mV improvement by NBL, and 0.47 VMIN for the 128 Mb 6T-HP with 40 mV improvement by the DNR. Improved VMIN reduces 45.4% and 12.2% power-consumption of the SRAM macro with the help of each assist circuit, respectively.

_{\rm MIN}

In a 0.13-/spl mu/m CMOS logic compatible process, a 256K /spl times/ 32 bit (8 Mb) local SONOS embedded flash EEPROM was implemented using the ATD-assisted current sense amplifier (AACSA) for 0.9 V (0.7 /spl sim/ 1.4 V) low V/sub CC/ application. Read operation is performed at a high frequency of 66 MHz and shows a low current of typically 5 mA at 66-MHz operating frequency. Program operation is performed for common source array with wide I/Os (/spl times/32) by using the data-dependent source bias control scheme (DDSBCS). This novel local SONOS embedded flash EEPROM core has the cell size of 0.276 /spl mu/m/sup 2/ (16.3 F/sup 2//bit) and the program and erase time of 20 /spl mu/s and 20 ms, respectively.

Enhancement Techniques for Low-Power Applications

The power consumption of a mobile application processor (AP) is strongly limited by the SRAM minimum operating voltage, VMIN [1], since the 6T bit cell must balance between write-ability and bit cell stability. However, the SRAM VMIN scales down gradually with advanced process nodes due to increased variability. This is evident with the quantized device-width and limited process-knobs of a FinFET technology, which has greatly affected SRAM design [2-4]. Therefore, assist-circuits are more crucial in a FinFET technology to improve VMIN, which in turn adds to the Power, Performance, and Area (PPA) gain of SRAM.

A 130-nm 0.9-V 66-MHz 8-Mb (256K /spl times/ 32) local SONOS embedded flash EEPROM

A trip-point bit-line precharge (TBP) sensing scheme is proposed for high-speed single-ended static random-access memory (SRAM). This TBP scheme mitigates the issues of limited performance, power, sensing margin, and area found in the previous single-ended SRAM sensing schemes by biasing the bit-line to a slightly larger value than the trip point of the sense amplifier. Simulation results show that the TBP sensing scheme can reduce the sensing time by 58.5% and 10% compared with the domino and ac-coupled sensing schemes, respectively. Further, compared with the ac-coupled sensing scheme, the proposed scheme offers 10% lower sensing power, 36% lesser area, and a 60 mV lower value of the minimum supply voltage for the target sensing yield.

17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization

An offset-compensated cross-coupled PFET bit-line (BL) conditioning circuit (OC-CPBC) and a selective negative BL write-assist circuit (SNBL-WA) are proposed for high-density FinFET static RAM (SRAM). The word-line (WL) underdrive read-assist and the negative BL write-assist circuits should be used for the stable operation of high-density FinFET SRAM. However, the WL underdrive read-assist circuit degrades the performance, and the negative BL write-assist circuit consumes a large amount of energy. The OC-CPBC enhances BL development during the evaluation phase by applying cross-coupled PFETs whose offset is compensated by precharging each of the two BLs separately through diode-connected cross-coupled PFETs. The SNBL-WA performs a write assist only when a write failure is detected, and this selective write assist reduces the write energy consumption. The simulation results show that the performance and energy consumption are improved by 41% and 48%, respectively, by applying the OC-CPBC and SNBL-WA to SRAM, even with a decrease in area.

Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM

For the first time, a novel robust (square-shape cylinder type) TiN/AHO (Al/sub 2/O/sub 3/-HfO/sub 2/)/TiN capacitor with Co-silicide on landing cell pad suitable for both stand-alone and embedded DRAMs are successfully developed with 88nm (pitch 176nm) feature size, which is the smallest feature size ever reported in DRAM technology, using ArF lithography for aiming 70nm stand-alone and embedded DRAM technology. The capacitor with Toxeq of 1.5nm and leakage current of less than 1 fA/cell is achieved. The cell contact resistance is greatly improved by using Co-silicidation on landing cell pad and metal storage node contact plug, which results in high performance.

Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM

We present the discharge characteristics of a rare gas halide mixture in AC- Plasma Display Panels. Studies for excimer gas of plasma display panels are performed using XeF. This excimer gas is investigated as function of its pressure and different discharge condition. In this paper, the real panel using XeF excimer gas is researched for good discharge characteristics and a full-color panel is demonstrated.

A novel robust TiN/AHO/TiN capacitor and CoSi/sub 2/ cell pad structure for 70nm stand-alone and embedded DRAM technology and beyond

A switching pMOS sense amplifier (SPSA) is proposed for high-speed single-ended static RAM sensing. By using the same pull-up pMOS transistor for sensing and precharging the bit-line, the performance is enhanced, and the power consumption is reduced. A keeper that compensates bit-line leakage is also employed, and a minimum operating voltage of 0.51 V is obtained. Compared to the previous dynamic pMOS sense amplifier and AC-coupled sense amplifier (ACSA), the sensing time is improved by 55% and 10%, respectively, and the power consumption is reduced by 12% and 44%, respectively. Furthermore, the area of the SPSA is estimated to be 43% smaller than that of the ACSA. Although the SPSA has a 59% larger area than a dynamic pMOS sense amplifier, the area overhead can be mitigated by allocating a larger number of cells per bit-line (CpBL) because the performance of the SPSA is still better than that of the dynamic pMOS, even with a CpBL that is two times larger.

P-50: Excimer Gas Discharge Characteristics for Color AC-PDPs

With the explosive growth of battery-operated portable devices, the demand for low power and small size has been increasing for system-on-a-chip (SoC). The FinFET is considered as one of the most promising technologies for future low-power mobile applications because of its good scaling ability, high on-current, better SCE and subthreshold slope, and small leakage current [1]. As a key approach for low-power, supply-voltage (VDD) scaling has been widely used in SoC design. However, SRAM is the limiting factor of voltage-scaling, since all SRAM functions of read, write, and hold-stability are highly influenced by increased variations at low VDD, resulting in lower yield. In addition, the width-quantization property of FinFET device reduces the design window for transistor sizing, and increases the failure probability due to the un-optimized bitcell sizing [1]. In order to overcome the bitcell challenges to high yield, peripheral-assist techniques are required. In this paper, we present 14nm FinFET-based 128Mb 6T SRAM chips featuring low-VMIN with newly developed assist techniques.

Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM

A latch-type sense amplifier (SA) utilizing adaptive resistance technique is proposed. With adaptively adjusted resistance in a latch path, the proposed SA can compensate for an erroneous voltage drop in bit-lines induced by bit-cell leakage current. The simulation shows that the sense amplifier margin (SM) is improved in the presence of mismatches. The SA test chip is fabricated in a 0.18-μm CMOS technology showing the SM improvement of 6% to 15% at various supply voltages.